公开(公告)号：US11342907B2

公开(公告)日：2022-05-24

申请号：US16866871

申请日：2020-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungi Seok ,  Seungjin Kim ,  Byungki Han ,  Jaehoon Lee

IPC: H03K5/1534 ,  H03K3/017 ,  H03K5/151 ,  H03K5/24

Abstract: An electronic device includes: a first equalizing circuit configured to receive a data signal and output a first equalizing signal based on the data signal; a pulse generator configured to generate a first pulse signal and a second pulse signal in response to a rising edge and a falling edge of the data signal, respectively; a second equalizing circuit configured to output a second equalizing signal based on the first pulse signal and the second pulse signal that have been inverted; and an output terminal configured to output an output signal in which the first equalizing signal and the second equalizing signal have been summed.

公开(公告)号：US09698757B2

公开(公告)日：2017-07-04

申请号：US14908067

申请日：2014-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungki Han ,  Suseob Ahn ,  Jongwoo Lee

IPC: H03H11/12 ,  H03H11/04 ,  H04L25/03 ,  H03H7/24

CPC classification number: H03H11/12 ,  H03H7/24 ,  H03H11/0405 ,  H03H11/0455 ,  H03H11/1252 ,  H03H11/1291 ,  H03H2011/0494 ,  H03H2250/00 ,  H04L25/03

Abstract: The ABB blocks 332, 334, 336, and 318 are configured to process the I/Q signals corresponding to the first or the second HB independently or the I/Q signals corresponding to the LB in cooperation by two. In detail, the first ABB I block 332 and the first ABB Q block 334 operate independently in the 3G/4G mode but they are configured to process the I signal (or Q signal) of the LB in the 2G mode. Likewise, the second ABB Q block 336 and the second ABB I block 318 operate independently in the 3G/4G mode but they are configured to process the Q signal (or I signal) of the LB in the 2G mode. The first ABB I/Q blocks 332 and 334 and the second ABB I/Q blocks 336 and 318 are arranged symmetrically to processing the I/Q signals cooperatively in the 2G mode. In detail, the second ABB Q block 336 is arranged close to the first ABB Q block 334 such that the capacitor regions included in the first ABB I/Q blocks 332 and 334 are connected to each other and the capacitor regions included in the second ABB I/Q blocks 336 and 338 are connected to each other.

公开(公告)号：US11057040B2

公开(公告)日：2021-07-06

申请号：US17006152

申请日：2020-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehong Jung ,  Sangdon Jung ,  Kyungmin Lee ,  Byungki Han

IPC: H03L7/081 ,  H03L7/091 ,  H03L7/197 ,  H03L7/099

Abstract: A phase-locked loop (PLL) circuit may include a voltage-controlled oscillator, a sub-sampling PLL circuit, and a fractional frequency division control circuit. The fractional frequency division control circuit may include a voltage-controlled delay line that routes a feedback signal to generate delay information, a replica voltage-controlled delay line to which the delay information is applied and configured to route a reference clock signal to generate a plurality of delay reference clock signals each delayed by up to a different respective delay time, and a digital-to-time converter (DTC) configured to generate the selection reference clock signal from the plurality of delay reference clock signals and output the selection reference clock signal to the sub-sampling PLL circuit.