公开(公告)号：US20240321823A1

公开(公告)日：2024-09-26

申请号：US18531883

申请日：2023-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donguk Kwon ,  Gongmyeong Kim ,  Sunchul Kim ,  Chaein Moon ,  Hyeonrae Cho

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/83 ,  H01L21/481 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/18 ,  H10B80/00 ,  H01L24/48 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16227 ,  H01L2224/32237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/014 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/1443

Abstract: Provided is a semiconductor package with enhanced reliability and a method of manufacturing the same. The semiconductor package includes a package substrate including a body layer having a central area and a peripheral area, a first protective layer on a top surface of the body layer, and a second protective layer on the first protective layer in the peripheral area, a semiconductor chip mounted on the first protective layer in the central area in a flip-chip structure, an underfill in a gap between the first protective layer and the semiconductor chip and in a gap between the connection terminals, an interposer on the semiconductor chip, and inter-substrate connection terminals on the peripheral area of the package substrate and electrically connecting the package substrate to the interposer, where the underfill has an anchor structure extending into the first protective layer.

公开(公告)号：US20250079373A1

公开(公告)日：2025-03-06

申请号：US18740596

申请日：2024-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chaein Moon

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a substrate including an insulating layer and a plurality of first pads on the insulating layer; a semiconductor chip including a plurality of second pads electrically connected to at least a portion of the plurality of first pads, the plurality of second pads overlapping the at least a portion of the plurality of first pads in a first direction; and a plurality of bumps on one surface of the substrate or one surface of the semiconductor chip, each of which has at least a portion having a melting point lower than a melting point of each of the plurality of first pads and a melting point of each of the plurality of second pads, wherein the plurality of bumps include a plurality of first bumps electrically connected to at least a portion of the plurality of first pads or at least a portion of the plurality of second pads, and at least one second bump having a permeability higher than a permeability of each of the plurality of first bumps.

公开(公告)号：US20240128229A1

公开(公告)日：2024-04-18

申请号：US18337860

申请日：2023-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungkeun Kang ,  Chaein Moon ,  Youngja Kim ,  Youngmin Lee

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L2224/75272 ,  H01L2224/75704 ,  H01L2224/75803 ,  H01L2224/75804 ,  H01L2924/40

Abstract: A solder reflow apparatus may include a reflow chamber, a heater and a stage. The reflow chamber may be configured to receive a heat transfer fluid. The heat transfer fluid may be configured for transferring heat to a solder for mounting an electronic part on a substrate. The heater may be configured to heat the heat transfer fluid in the reflow chamber. The stage may be in the reflow chamber to support the substrate. The stage may be inclined to a bottom surface of the reflow chamber to induce the heat transfer fluid toward a central portion of the substrate. Thus, the vertically ascended heat transfer fluid may be uniformly applied to the central portion and an edge portion of the substrate so that the solders at the central portion and the edge portion of the substrate may be uniformly soldered.