公开(公告)号：US11521866B2

公开(公告)日：2022-12-06

申请号：US17198938

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Yoon Song ,  Chan-Hoon Park ,  Jong-Woo Sun ,  Jung-Mo Sung ,  Je-Woo Han ,  Jin-Young Park

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3065

Abstract: In a plasma processing method, a substrate is loaded onto a lower electrode within a chamber. A plasma power is applied to form plasma within the chamber. A voltage function of a nonsinusoidal wave having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function in order to control an ion energy distribution generated at a surface of the substrate. A bias power of the nonsinusoidal wave is applied to the lower electrode.

公开(公告)号：US09799561B2

公开(公告)日：2017-10-24

申请号：US15238836

申请日：2016-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Hoon Park ,  Dong-Chan Kim ,  Masayuki Tomoyasu ,  Je-Woo Han

IPC: H01L21/338 ,  H01L21/768 ,  H01L21/66 ,  H01L21/68 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/682 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L22/12 ,  H01L22/20 ,  H01L29/4983

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming a first interlayer insulating layer including a first trench that is defined by a first gate spacer and a second trench that is defined by a second gate spacer on a substrate, forming a first gate electrode that fills a part of the first trench and a second gate electrode that fills a part of the second trench, forming a first capping pattern that fills the remainder of the first trench on the first gate electrode, forming a second capping pattern that fills the remainder of the second trench on the second gate electrode, forming a second interlayer insulating layer that covers the first gate spacer and the second gate spacer on the first interlayer insulating layer, forming a third interlayer insulating layer on the second interlayer insulating layer and forming a contact hole that penetrates the third interlayer insulating layer and the second interlayer insulating layer between the first gate electrode and the second gate electrode.

公开(公告)号：US11037806B2

公开(公告)日：2021-06-15

申请号：US16509815

申请日：2019-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Yoon Song ,  Chan-Hoon Park ,  Jong-Woo Sun ,  Jung-Mo Sung ,  Je-Woo Han ,  Jin-Young Park

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3065

Abstract: In a plasma processing method, a substrate is loaded onto a lower electrode within a chamber. A plasma power is applied to form plasma within the chamber. A voltage function of a nonsinusoidal wave having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function in order to control an ion energy distribution generated at a surface of the substrate. A bias power of the nonsinusoidal wave is applied to the lower electrode.

公开(公告)号：US20200227289A1

公开(公告)日：2020-07-16

申请号：US16509815

申请日：2019-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Yoon Song ,  Chan-Hoon Park ,  Jong-Woo Sun ,  Jung-Mo Sung ,  Je-Woo Han ,  Jin-Young Park

IPC: H01L21/67 ,  H01J37/32

Abstract: In a plasma processing method, a substrate is loaded onto a lower electrode within a chamber. A plasma power is applied to form plasma within the chamber. A voltage function of a nonsinusoidal wave having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function in order to control an ion energy distribution generated at a surface of the substrate. A bias power of the nonsinusoidal wave is applied to the lower electrode.

公开(公告)号：US20130285019A1

公开(公告)日：2013-10-31

申请号：US13833987

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

Inventor： Dongwon KIM ,  Dae Mann Kim ,  Yoon-Ha Jeong ,  Sooyoung Park ,  Chan-Hoon Park ,  Rock-Hyun Baek ,  Sang-Hyun Lee

IPC: H01L29/775 ,  H01L29/78

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/78 ,  Y10S977/742

Abstract: Provided is a field effect transistor including a drain region, a source region, and a channel region. The field effect transistor may further include a gate electrode on or surrounding at least a portion of the channel region, and a gate dielectric layer between the channel region and the gate electrode. A portion of the channel region adjacent the source region has a sectional area smaller than that of another portion of the channel region adjacent the drain region.

Abstract translation: 提供了包括漏极区域，源极区域和沟道区域的场效应晶体管。 场效应晶体管还可以包括在沟道区的至少一部分上或围绕沟道区的至少一部分的栅电极，以及沟道区和栅电极之间的栅介质层。 与源极区域相邻的沟道区域的一部分的截面积小于与漏极区域相邻的沟道区域的另一部分的截面面积。