公开(公告)号：US20140367774A1

公开(公告)日：2014-12-18

申请号：US14294412

申请日：2014-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ryeol Yoo ,  Jun-Noh Lee ,  Dong-Chan Kim ,  Han-Jin Lim

IPC: H01L29/423 ,  H01L29/49

CPC classification number: H01L29/4236 ,  H01L27/10876 ,  H01L29/4966 ,  H01L29/4983

Abstract: Semiconductor devices are provided including a first trench in a semiconductor substrate; a first insulating film in the first trench; a first conductive film on the first insulating film, the first conductive film having upper and lower portions and filling at least a portion of the first trench; and a first work function adjustment film having first and second portions, a first lower work function adjustment film portion and a first upper work function adjustment portion. The first lower work function adjustment film portion overlaps the lower portion of the first conductive film and the first upper work function adjustment film portion overlaps the upper portion of the first conductive film between the first insulating film and the first conductive film.

Abstract translation: 提供半导体器件，其包括半导体衬底中的第一沟槽; 第一沟槽中的第一绝缘膜; 在所述第一绝缘膜上的第一导电膜，所述第一导电膜具有上部和下部并填充所述第一沟槽的至少一部分; 以及具有第一和第二部分的第一功能调整膜，第一下部功能调整膜部分和第一上部功能调整部分。 第一下功函数调整膜部与第一导电膜的下部重叠，第一上功函调整膜部与第一绝缘膜与第一导电膜之间的第一导电膜的上部重叠。

公开(公告)号：US10910266B2

公开(公告)日：2021-02-02

申请号：US16295751

申请日：2019-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Hoon Choi ,  Ja-Eung Koo ,  Kwan-Sik Kim ,  Dong-Chan Kim ,  Il-Young Yoon ,  Man-Geun Cho

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L27/30 ,  H01L27/146 ,  H01L21/321

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

公开(公告)号：US10283204B2

公开(公告)日：2019-05-07

申请号：US15607551

申请日：2017-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Min Choi ,  Dong-Chan Kim ,  Ae-Jeong Lee ,  Moo-Rym Choi

IPC: G06F12/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/22 ,  G11C16/34

Abstract: In a method of operating a nonvolatile memory device, a first sub-block to be erased is selected in a first memory block including the first sub-block and a second sub-block adjacent to the first sub-block, in response to a erase command and an address. The first sub-block includes memory cells connected to a plurality of word-lines including at least one boundary word-line adjacent to the second sub-block and internal word-lines other than the at least one boundary word-line. An erase voltage is applied to a substrate in which the first memory block is formed. Based on a voltage level of the erase voltage applied to the substrate, applying, a first erase bias condition to the at least one boundary word-line and a second erase bias condition different from the first erase bias condition to the internal word-lines during an erase operation being performed on the first sub-block.

公开(公告)号：US09799561B2

公开(公告)日：2017-10-24

申请号：US15238836

申请日：2016-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Hoon Park ,  Dong-Chan Kim ,  Masayuki Tomoyasu ,  Je-Woo Han

IPC: H01L21/338 ,  H01L21/768 ,  H01L21/66 ,  H01L21/68 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/682 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L22/12 ,  H01L22/20 ,  H01L29/4983

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming a first interlayer insulating layer including a first trench that is defined by a first gate spacer and a second trench that is defined by a second gate spacer on a substrate, forming a first gate electrode that fills a part of the first trench and a second gate electrode that fills a part of the second trench, forming a first capping pattern that fills the remainder of the first trench on the first gate electrode, forming a second capping pattern that fills the remainder of the second trench on the second gate electrode, forming a second interlayer insulating layer that covers the first gate spacer and the second gate spacer on the first interlayer insulating layer, forming a third interlayer insulating layer on the second interlayer insulating layer and forming a contact hole that penetrates the third interlayer insulating layer and the second interlayer insulating layer between the first gate electrode and the second gate electrode.

公开(公告)号：US20150228786A1

公开(公告)日：2015-08-13

申请号：US14542867

申请日：2014-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wook-Yeol Yi ,  Ki-Hong Nam ,  Dong-Chan Kim ,  Hee-Don Hwang ,  Young-Min Kim ,  Duk-Young Jang

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7843 ,  H01L21/76224 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7846

Abstract: A semiconductor device includes a semiconductor substrate having an active region. A gate trench is disposed to cross the active region. First and second source/drain regions are disposed in the active region at both sides of the gate trench. A gate electrode is disposed in the gate trench. A gate dielectric layer is disposed between the gate electrode and the active region. A stress pattern is disposed on the gate electrode and in the gate trench. The stress pattern has a lower residual stress than silicon nitride.

Abstract translation: 半导体器件包括具有有源区的半导体衬底。 栅极沟槽被布置成越过有源区域。 第一和第二源极/漏极区域设置在栅极沟槽的两侧的有源区域中。 栅电极设置在栅极沟槽中。 栅电介质层设置在栅电极和有源区之间。 应力图案设置在栅极电极和栅极沟槽中。 应力模式比氮化硅具有更低的残余应力。

公开(公告)号：US09054037B2

公开(公告)日：2015-06-09

申请号：US14060806

申请日：2013-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Chan Kim ,  Tai-Su Park ,  Ju-Eun Kim ,  Ki-Hong Nam

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/51 ,  H01L21/02 ,  H01L27/108

CPC classification number: H01L21/28185 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/28194 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/513 ,  H01L29/517

Abstract: A method of fabricating a semiconductor device includes forming a trench in a substrate, forming a pre-gate insulating film along side surfaces and a bottom surface of the trench, and oxidizing the pre-gate insulating film through a densification process.

Abstract translation: 制造半导体器件的方法包括在衬底中形成沟槽，沿着沟槽的侧表面和底表面形成预栅绝缘膜，并通过致密化过程来氧化预栅绝缘膜。

公开(公告)号：US11361995B2

公开(公告)日：2022-06-14

申请号：US17146597

申请日：2021-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Hoon Choi ,  Ja-Eung Koo ,  Kwan-Sik Kim ,  Dong-Chan Kim ,  Il-Young Yoon ,  Man-Geun Cho

IPC: H01L21/768 ,  H01L21/321 ,  H01L27/146 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L27/30

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

公开(公告)号：US20210166976A1

公开(公告)日：2021-06-03

申请号：US17146597

申请日：2021-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Hoon Choi ,  Ja-Eung Koo ,  Kwan-Sik Kim ,  Dong-Chan Kim ,  Il-Young Yoon ,  Man-Geun Cho

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L27/30 ,  H01L21/321

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.