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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240431122A1

    公开(公告)日：2024-12-26

    申请号：US18623732

    申请日：2024-04-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hongjun LEE ,  Kiseok LEE ,  Hyungeun CHOI ,  Keunnam KIM ,  Incheol NAM

    IPC: H10B80/00 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor device includes a lower chip structure, and an upper chip structure on the lower chip structure. The lower chip structure includes a memory structure, a lower interconnection structure electrically connected to the memory structure, and a lower bonding pad electrically connected to the lower interconnection structure. The upper chip structure includes an upper base, a peripheral transistor on the upper base, a first upper interconnection structure electrically connected to the peripheral transistor, on the upper base, a through-via penetrating through the upper base and electrically connected to the first upper interconnection structure, an upper bonding pad bonded to the lower bonding pad, below the upper base, and an intermediate connection structure electrically connecting the upper bonding pad and the through-via, between the upper base and the lower chip.

    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230320076A1

    公开(公告)日：2023-10-05

    申请号：US17983489

    申请日：2022-11-09

    Applicant: Samsung Electronics Co., LTD.

    Inventor： HYO-SUB KIM ,  Kseok LEE ,  Myeong-Dong LEE ,  Jongmin KIM ,  Hui-Jung KIM ,  Jihun LEE ,  Hongjun LEE

    IPC: H01L27/108 ,  G11C5/06

    CPC classification number: H01L27/10814 ,  G11C5/063

    Abstract: A semiconductor memory device includes: a device isolation pattern provided on a substrate to provide a first active portion and a second active portion; a first storage node pad disposed on the first active portion; a second storage node pad disposed on the second active portion; a pad separation pattern disposed between the first and second storage node pads; a word line disposed in the substrate to cross the first and second active portions; a bit line disposed on the pad separation pattern and crossing the word line; a buffer layer disposed on the pad separation pattern; and a mask polysilicon pattern interposed between the buffer layer and the bit line, wherein a side surface of the mask polysilicon pattern is substantially aligned to a side surface of the bit line, and the mask polysilicon pattern is vertically overlapped with the pad separation pattern.

    SEMICONDUCTOR DEVICE INCLUDING VERTICAL ACTIVE PILLAR
    3.
    发明公开
    SEMICONDUCTOR DEVICE INCLUDING VERTICAL ACTIVE PILLAR 审中-公开

    公开(公告)号：US20240276712A1

    公开(公告)日：2024-08-15

    申请号：US18435263

    申请日：2024-02-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hongjun LEE ,  Keunnam KIM ,  Kiseok LEE

    IPC: H10B12/00 ,  H01L29/78

    CPC classification number: H10B12/482 ,  H01L29/7827

    Abstract: A semiconductor device may include a substrate, a bit line structure, first and second gate electrodes spaced apart from each other, and first and second gate dielectric layers. The substrate may include a first upper active region and a second upper active region spaced apart from each other and protruding upwardly from a lower active region, a first vertical active pillar protruding upwardly from the first upper active region, and a second vertical active pillar protruding upwardly from the second upper active region. The bit line structure may be between the first and second upper active regions. The first and second gate electrodes respectively may surround channel regions of the first and second vertical active pillars. First and second gate dielectric layers respectively may be between the first vertical active pillar and the first gate electrode and between the second vertical active pillar and the second gate electrode.

    SEMICONDUCTOR DEVICE
    5.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240341081A1

    公开(公告)日：2024-10-10

    申请号：US18388295

    申请日：2023-11-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hongjun LEE ,  Keunnam KIM ,  Seungmuk KIM ,  Kiseok LEE

    IPC: H10B12/00 ,  G11C5/06

    CPC classification number: H10B12/315 ,  G11C5/063 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

    Abstract: A semiconductor device which includes a semiconductor substrate having a cell area and a peripheral area, the peripheral area including a first area and a second area adjacent to each other, first transistors on the first area, a first wiring layer on the first transistors, a first pad on the second area and a portion of the first area, a first contact plug between the first wiring layer and the first area, a second contact plug between the first pad and the first area, a second pad on the first wiring layer, a third contact plug between the second pad and the first wiring layer, and a plurality of first capacitors on the second pad and that vertically overlap the first transistors, thus reliability and electrical characteristics of the semiconductor device may be increased.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220352173A1

    公开(公告)日：2022-11-03

    申请号：US17558728

    申请日：2021-12-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hongjun LEE ,  Kyungsun RYU ,  Dongjun LEE ,  Jin-Seong LEE

    IPC: H01L27/108

    Abstract: A semiconductor device includes bit lines extending in a first direction on a substrate, a lower contact connected to the substrate between two adjacent ones of the bit lines, a landing pad on the lower contact, and an insulating structure surrounding a sidewall of the landing pad, the insulating structure including a first insulating pattern having a top surface at a lower level than a top surface of the landing pad, and a second insulating pattern on the top surface of the first insulating pattern.

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