公开(公告)号：US20230165008A1

公开(公告)日：2023-05-25

申请号：US18045971

申请日：2022-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbum KIM ,  Sunghoon KIM ,  Daeseok BYEON

IPC: H01L27/11573 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/08

CPC classification number: H01L27/11573 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/08

Abstract: A memory device includes a first lower semiconductor layer and a second lower semiconductor layer. The first lower semiconductor layer is disposed below a first upper semiconductor layer including a first memory cell array. The first lower semiconductor layer includes a first page buffer electrically connected to the first memory cell array. The second lower semiconductor layer is disposed below a second upper semiconductor layer includes a second memory cell array and disposed adjacent to the first upper semiconductor layer in a first direction. The second lower semiconductor layer includes a first portion of a second page buffer electrically connected to the second memory cell array and being disposed adjacent to the first lower semiconductor layer in the first direction. The first lower semiconductor layer further includes a second portion of the second page buffer different from the first portion.

公开(公告)号：US20230039507A1

公开(公告)日：2023-02-09

申请号：US17721574

申请日：2022-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbum KIM ,  Sunghoon KIM

IPC: H01L27/11573 ,  G11C16/24 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A semiconductor device includes a cell region and a peripheral circuit region. The cell region includes gate electrode layers stacked on a substrate, channel structures extending in a first direction, extending through the gate electrode layers, and connected to the substrate, and bit lines extending in a second direction and connected to the channel structures above the gate electrode layers. The peripheral circuit region includes page buffers connected to the bit lines. Each page buffer includes a first and second elements adjacent to each other in the second direction and sharing a common active region between a first gate structure of the first element and a second gate structure of the second element in the second direction. Boundaries of the common active region include an oblique boundary extending in an oblique direction forming an angle between 0 and 90 degrees with the second direction.

公开(公告)号：US20240242755A1

公开(公告)日：2024-07-18

申请号：US18423583

申请日：2024-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbum KIM ,  Sunghoon KIM

IPC: G11C11/4093 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4093 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

Abstract: A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer arranged in the vertical direction. A first semiconductor layer includes a plurality of memory cells, and a plurality of metal lines extending in a first direction, and including first bit lines, second bit lines, and a common source line tapping wire between the first bit lines and the second bit lines. A second semiconductor layer includes a page buffer circuit connected to the first bit lines and the second bit lines, and the page buffer circuit includes first transistors arranged below the first bit lines and electrically connected to the first bit lines, second transistors arranged below the second bit lines and electrically connected to the second bit lines, and a first guard ring arranged below and overlapped the common source line tapping wire in the vertical direction and extending in the first direction.

公开(公告)号：US20230010028A1

公开(公告)日：2023-01-12

申请号：US17574657

申请日：2022-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbum KIM ,  Sunghoon KIM

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4099 ,  G11C5/06

Abstract: A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer arranged in the vertical direction. A first semiconductor layer includes a plurality of memory cells, and a plurality of metal lines extending in a first direction, and including first bit lines, second bit lines, and a common source line tapping wire between the first bit lines and the second bit lines. A second semiconductor layer includes a page buffer circuit connected to the first bit lines and the second bit lines, and the page buffer circuit includes first transistors arranged below the first bit lines and electrically connected to the first bit lines, second transistors arranged below the second bit lines and electrically connected to the second bit lines, and a first guard ring arranged below and overlapped the common source line tapping wire in the vertical direction and extending in the first direction.

公开(公告)号：US20240055380A1

公开(公告)日：2024-02-15

申请号：US18231838

申请日：2023-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbum KIM ,  Cheonan Lee ,  Sukkang Sung

IPC: H01L23/00 ,  H01L25/065 ,  H10B43/35 ,  H10B41/35

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H10B43/35 ,  H10B41/35 ,  H10B80/00

Abstract: A semiconductor device includes: a first structure including a first substrate and a peripheral circuit disposed on the first substrate; and a second structure including a common source plate and a cell stack disposed on the common source plate and including a plurality of gate electrodes and channel structures, wherein the cell stack includes a plurality of cell blocks including a plurality of main blocks and at least one dummy block disposed at one side of the plurality of main blocks, wherein the common source plate includes a main common source line region and a dummy common source line region, wherein the main common source line region overlaps the plurality of main blocks, and the dummy common source line region is separated from the main common source line region and overlaps the at least one dummy block by being electrically isolated from the at least one dummy block.