公开(公告)号：US20190050352A1

公开(公告)日：2019-02-14

申请号：US16165139

申请日：2018-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changho Yun ,  Sung-Joon Kim

IPC: G06F13/16 ,  G11C11/406

CPC classification number: G06F13/1689 ,  G11C5/04 ,  G11C7/1084 ,  G11C11/406 ,  G11C29/00 ,  G11C2207/2254

Abstract: A memory system includes a first dual in-line memory module (DIMM), a second DIMM, and a controller. The first DIMM may include a first memory device including a first on-die termination (ODT) circuit connected to a data line. The second DIMM may include a second memory device including a second ODT circuit connected to the data line. The controller is connected to the first and second memory devices through the data line, generates first and second delay information, and determines whether to change an ODT duration of the first or second ODT circuit using the first and second delay information. The first delay information is indicative of a time taken for command/address or clock signals to reach the first memory device. The second delay information is indicative of a time taken for command/address signal or clock signals to reach the second memory device.

公开(公告)号：US10733119B2

公开(公告)日：2020-08-04

申请号：US16165139

申请日：2018-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changho Yun ,  Sung-Joon Kim

IPC: G11C7/00 ,  G06F13/16 ,  G11C11/406 ,  G11C7/10 ,  G11C29/00 ,  G11C5/04

Abstract: A memory system includes a first dual in-line memory module (DIMM), a second DIMM, and a controller. The first DIMM may include a first memory device including a first on-die termination (ODT) circuit connected to a data line. The second DIMM may include a second memory device including a second ODT circuit connected to the data line. The controller is connected to the first and second memory devices through the data line, generates first and second delay information, and determines whether to change an ODT duration of the first or second ODT circuit using the first and second delay information. The first delay information is indicative of a time taken for command/address or clock signals to reach the first memory device. The second delay information is indicative of a time taken for command/address signal or clock signals to reach the second memory device.

公开(公告)号：US10108563B2

公开(公告)日：2018-10-23

申请号：US15659182

申请日：2017-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changho Yun ,  Sung-Joon Kim

IPC: G11C7/00 ,  G06F13/16 ,  G11C11/406

Abstract: A memory system includes a first dual in-line memory module (DIMM), a second DIMM, and a controller. The first DIMM may include a first memory device including a first on-die termination (ODT) circuit connected to a data line. The second DIMM may include a second memory device including a second ODT circuit connected to the data line. The controller is connected to the first and second memory devices through the data line, generates first and second delay information, and determines whether to change an ODT duration of the first or second ODT circuit using the first and second delay information. The first delay information is indicative of a time taken for command/address or clock signals to reach the first memory device. The second delay information is indicative of a time taken for command/address signal or clock signals to reach the second memory device.

公开(公告)号：US12158809B2

公开(公告)日：2024-12-03

申请号：US18295457

申请日：2023-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Young Lee ,  Sung-Joon Kim ,  Ilho Kim ,  Kyungjin Park ,  Changho Yun ,  Jinhun Jeong ,  Insu Choi ,  Kyung-Hee Han ,  Yukyoung Kim ,  Jinwoo Kim ,  Chaeeun Lee ,  Yunmi Hwang

IPC: G06F11/10 ,  G06F11/07

Abstract: Disclosed is an electronic device including a memory module that includes at least one dynamic random access memory, and a processor configured to access the memory module, determine a corrected error count associated with an address of a corrected error in response to the corrected error being detected when data are read from the memory module, read an error log associated with the corrected error, determine a risk level of the corrected error based on the error log, and schedule a post package repair (PPR) for the address of the corrected error in response to the risk level of the corrected error being high.

公开(公告)号：US20240168846A1

公开(公告)日：2024-05-23

申请号：US18328959

申请日：2023-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinhun JEONG ,  Sung-Joon Kim ,  Ilho Kim ,  Kyungjin Park ,  Changho Yun ,  Ho-Young Lee ,  Jongwon Jeong ,  Insu Choi ,  Kyung-Hee Han ,  Yunmi Hwang

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/14

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/1438

Abstract: A method for preparing error recovery of a memory device included in a memory system includes performing a training operation of the memory device upon power-on of the memory system, booting an operating system into a normal mode by operating the memory device using a selected operation frequency of a plurality of operation frequencies based on results of the training operation, detecting an error frequency among the plurality of operation frequencies in response to a change of the selected operation frequency of the memory device by the operating system, the error frequency being an operation frequency which causes at least one error in the memory device, and storing information regarding the detected error frequency in a first register included in a memory controller associated with the memory device.