公开(公告)号：US09502342B2

公开(公告)日：2016-11-22

申请号：US14801110

申请日：2015-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilho Kim

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56 ,  H01L25/10 ,  H01L23/42 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A method of fabricating a package-on-package (PoP) type of semiconductor package may include providing a lower package with a lower substrate, a lower semiconductor chip, and a lower mold layer and providing an upper package with an upper substrate, an upper semiconductor chip, and an upper mold layer. A through hole is formed to penetrate the upper package, and the upper package and lower package are electrically connected. A thermal interface material is injected into the through hole to form a first heat transmission part between, and in contact with, the upper package and the lower package.

Abstract translation: 制造封装封装（PoP）类型的半导体封装的方法可以包括提供具有下基板，下半导体芯片和下模层的下封装，并向上封装提供上基板，上基板 半导体芯片和上模层。 形成贯通上部封装的通孔，上部封装和下部封装电连接。 将热界面材料注入到通孔中以在上部包装和下部包装之间形成第一传热部分，并与之接触。

公开(公告)号：US20250039565A1

公开(公告)日：2025-01-30

申请号：US18772480

申请日：2024-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hosuk Han ,  Ilho Kim

IPC: H04N25/40 ,  H04N23/80 ,  H04N25/42

Abstract: An image processing circuit is provided. The image processing circuit includes a scan conversion controller configured to receive images from a plurality of channels connected to a plurality of imaging devices and to generate output data and an image signal processor configured to receive and process the output data from the scan conversion controller. The scan conversion controller is configured to determine a scan method for generating the output data according to a first operation mode or a second operation mode.

公开(公告)号：US09947554B2

公开(公告)日：2018-04-17

申请号：US15345534

申请日：2016-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonseok Choi ,  Ilho Kim ,  Changho Kim

IPC: H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/373 ,  H01L23/31

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/373 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68318 ,  H01L2221/68386 ,  H01L2224/02331 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2924/3511

Abstract: A support substrate, a method of manufacturing a semiconductor package, and a semiconductor package, the support substrate including a first plate; a second plate on the first plate; and an adhesive layer between the first plate and the second plate, wherein a coefficient of thermal expansion (CTE) of the adhesive layer is higher than a CTE of the first plate and higher than a CTE of the second plate.

公开(公告)号：US12218065B2

公开(公告)日：2025-02-04

申请号：US17697243

申请日：2022-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeohoon Yoon ,  Ilho Kim

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package may include a first semiconductor chip, a second semiconductor chip spaced apart from the first semiconductor chip, an adhesive layer including an interposition portion and a side portion, and a molding layer. The molding layer may surround the first semiconductor chip, the second semiconductor chip, and the adhesive layer. The interposition portion may be between the first and second semiconductor chips. The side portion may contact a side surface of the first semiconductor chip and a side surface of the second semiconductor chip. A top surface of the side portion is curved, and an outer side surface of the side portion is flat.

公开(公告)号：US20160111396A1

公开(公告)日：2016-04-21

申请号：US14801110

申请日：2015-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ilho Kim

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/36 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A method of fabricating a package-on-package (PoP) type of semiconductor package may include providing a lower package with a lower substrate, a lower semiconductor chip, and a lower mold layer and providing an upper package with an upper substrate, an upper semiconductor chip, and an upper mold layer. A through hole is formed to penetrate the upper package, and the upper package and lower package are electrically connected. A thermal interface material is injected into the through hole to form a first heat transmission part between, and in contact with, the upper package and the lower package.

Abstract translation: 制造封装封装（PoP）类型的半导体封装的方法可以包括提供具有下基板，下半导体芯片和下模层的下封装，并向上封装提供上基板，上基板 半导体芯片和上模层。 形成贯通上部封装的通孔，上部封装和下部封装电连接。 将热界面材料注入到通孔中以在上部包装和下部包装之间形成第一传热部分，并与之接触。

公开(公告)号：US12158809B2

公开(公告)日：2024-12-03

申请号：US18295457

申请日：2023-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Young Lee ,  Sung-Joon Kim ,  Ilho Kim ,  Kyungjin Park ,  Changho Yun ,  Jinhun Jeong ,  Insu Choi ,  Kyung-Hee Han ,  Yukyoung Kim ,  Jinwoo Kim ,  Chaeeun Lee ,  Yunmi Hwang

IPC: G06F11/10 ,  G06F11/07

Abstract: Disclosed is an electronic device including a memory module that includes at least one dynamic random access memory, and a processor configured to access the memory module, determine a corrected error count associated with an address of a corrected error in response to the corrected error being detected when data are read from the memory module, read an error log associated with the corrected error, determine a risk level of the corrected error based on the error log, and schedule a post package repair (PPR) for the address of the corrected error in response to the risk level of the corrected error being high.

公开(公告)号：US20240168846A1

公开(公告)日：2024-05-23

申请号：US18328959

申请日：2023-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinhun JEONG ,  Sung-Joon Kim ,  Ilho Kim ,  Kyungjin Park ,  Changho Yun ,  Ho-Young Lee ,  Jongwon Jeong ,  Insu Choi ,  Kyung-Hee Han ,  Yunmi Hwang

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/14

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/1438

Abstract: A method for preparing error recovery of a memory device included in a memory system includes performing a training operation of the memory device upon power-on of the memory system, booting an operating system into a normal mode by operating the memory device using a selected operation frequency of a plurality of operation frequencies based on results of the training operation, detecting an error frequency among the plurality of operation frequencies in response to a change of the selected operation frequency of the memory device by the operating system, the error frequency being an operation frequency which causes at least one error in the memory device, and storing information regarding the detected error frequency in a first register included in a memory controller associated with the memory device.

公开(公告)号：US20230021362A1

公开(公告)日：2023-01-26

申请号：US17714714

申请日：2022-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeohoon YOON ,  Ilho Kim

IPC: H01L23/00

Abstract: A semiconductor package is provided. The semiconductor package includes a redistribution structure having a front surface and a rear surface opposite the front surface, the redistribution structure including an insulating layer and a redistribution conductor provided in the insulating layer; a semiconductor chip provided on the rear surface and including a connection pad electrically connected to the redistribution conductor; an encapsulant provided on at least a portion of the semiconductor chip; under-bump metal (UBM) vias extending from the redistribution conductor to the front surface of the redistribution structure within the insulating layer; UBM pads provided on the front surface of the redistribution structure to correspond to the UBM vias, respectively, and each UMB pad of the UBM pads having an exposed surface convexly protruding away from the front surface of the redistribution structure; and a metal bump provided on the UBM pads and contacting the exposed surface of each UMB pad of the UBM pads.