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公开(公告)号:US20240212782A1
公开(公告)日:2024-06-27
申请号:US18226340
申请日:2023-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Changho YUN , Sungjoon KIM , Yukyoung KIM , Chaeeun Lee , Jongwon Jeong
CPC classification number: G11C29/46 , G11C29/1201 , G11C29/44
Abstract: A memory system including: a memory module including a plurality of memory chips; a mirror memory module including a plurality of mirror memory chips corresponding to the plurality of memory chips, a first mirror memory chip of the plurality of mirror memory chips being storing same data as a first memory chip of the plurality of memory chips; and a memory controller configured to, in a system running state in which an operation according to a request of a user is capable of being performed after the memory system is booted, provide the memory module with a command for instructing a normal operation to be performed and provide the mirror memory module with a command for instructing a memory built-in self-test (MBIST) to be performed.
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2.
公开(公告)号:US20240168846A1
公开(公告)日:2024-05-23
申请号:US18328959
申请日:2023-06-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinhun JEONG , Sung-Joon Kim , Ilho Kim , Kyungjin Park , Changho Yun , Ho-Young Lee , Jongwon Jeong , Insu Choi , Kyung-Hee Han , Yunmi Hwang
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/1438
Abstract: A method for preparing error recovery of a memory device included in a memory system includes performing a training operation of the memory device upon power-on of the memory system, booting an operating system into a normal mode by operating the memory device using a selected operation frequency of a plurality of operation frequencies based on results of the training operation, detecting an error frequency among the plurality of operation frequencies in response to a change of the selected operation frequency of the memory device by the operating system, the error frequency being an operation frequency which causes at least one error in the memory device, and storing information regarding the detected error frequency in a first register included in a memory controller associated with the memory device.
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