公开(公告)号：US20230420034A1

公开(公告)日：2023-12-28

申请号：US18045846

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyoung Lee ,  Kyu-Chang Kang ,  Donghak Shin ,  Hyun-Chul Yoon

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

CPC classification number: G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

Abstract: In a sense amplifier circuit, a first transistor is electrically connected between a first bitline and a first node, a first inverter includes a first input terminal and a first output terminal connected to the first node, and a second inverter includes a second input terminal connected to a second node and a second output terminal. A second transistor is electrically connected between the first output terminal and the second node, and a third transistor is electrically connected between the second output terminal and the first node. A precharge circuit transfers a first voltage to the first and second nodes during a first period, and transfers a second voltage higher than the first voltage to the first and second nodes during a second period.

公开(公告)号：US20130176803A1

公开(公告)日：2013-07-11

申请号：US13661773

申请日：2012-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ho Lee ,  Kyu-Chang Kang ,  Hyo-Chang Kim ,  Jae-Youn Youn ,  Sang-Jae Rhee

IPC: G11C11/402 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C7/08 ,  G11C11/40626 ,  G11C11/4091 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: A semiconductor memory device and a self-refresh method of the semiconductor memory device. The semiconductor memory device includes: a memory cell array including one or more memory cells; a sense amplifier connected to a sensing line and a complementary sensing line and sensing/amplifying data stored in the one or more memory cells; and a sense amplifier control circuit sequentially supplying a first voltage and a second voltage having different levels to the sense amplifier through the sensing line during a refresh operation.

Abstract translation: 半导体存储器件和半导体存储器件的自刷新方法。 半导体存储器件包括：包括一个或多个存储单元的存储单元阵列; 连接到感测线和互补感测线的感测放大器，以及感测/放大存储在所述一个或多个存储器单元中的数据; 以及读出放大器控制电路，其在刷新操作期间通过感测线路顺序地将具有不同电平的第一电压和第二电压提供给读出放大器。

公开(公告)号：US12237000B2

公开(公告)日：2025-02-25

申请号：US18045846

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyoung Lee ,  Kyu-Chang Kang ,  Donghak Shin ,  Hyun-Chul Yoon

IPC: G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C7/10

Abstract: In a sense amplifier circuit, a first transistor is electrically connected between a first bitline and a first node, a first inverter includes a first input terminal and a first output terminal connected to the first node, and a second inverter includes a second input terminal connected to a second node and a second output terminal. A second transistor is electrically connected between the first output terminal and the second node, and a third transistor is electrically connected between the second output terminal and the first node. A precharge circuit transfers a first voltage to the first and second nodes during a first period, and transfers a second voltage higher than the first voltage to the first and second nodes during a second period.

公开(公告)号：US09892779B2

公开(公告)日：2018-02-13

申请号：US15331970

申请日：2016-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Chang Kang ,  Hui-Kap Yang

IPC: G11C7/00 ,  G11C11/406 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/40618 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40603 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091

Abstract: A memory device includes a memory bank, a row selection circuit and a refresh controller. The memory bank includes a plurality of memory blocks, and each memory block includes a plurality of memory cells arranged in rows and columns. The row selection circuit performs an access operation with respect to the memory bank and a hammer refresh operation with respect to a row that is physically adjacent to a row that is accessed intensively. The refresh controller controls the row selection circuit such that the hammer refresh operation is performed during a row active time for the access operation. The hammer refresh operation may be performed efficiently and performance of the memory device may be enhanced by performing the hammer refresh operation during the row active time for the access operation.

公开(公告)号：US09287009B2

公开(公告)日：2016-03-15

申请号：US14595500

申请日：2015-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Chang Kang ,  Gil-Su Kim ,  Je-Min Ryu ,  Yun-Young Lee ,  Kyo-Min Sohn

IPC: G11C17/16 ,  G11C29/00 ,  G11C17/18

CPC classification number: G11C29/76 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/78 ,  G11C2029/4402

Abstract: A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.

Abstract translation: 修复电路包括第一和第二熔丝电路，确定电路和输出电路。 第一熔丝电路包括第一熔丝，并且被配置为产生指示第一熔丝是否已被编程的第一主信号。 第二熔丝电路包括第二保险丝，并且被配置为产生指示每个第二保险丝是否被编程的第一地址。 确定电路被配置为基于第一主信号和第一地址产生检测信号。 检测信号指示是否对第二熔丝电路执行了负编程操作。 输出电路被配置为基于第一主信号和检测信号产生第二主信号，并且基于第一地址和检测信号产生对应于有缺陷的输入地址的修复地址。