公开(公告)号：US20250169066A1

公开(公告)日：2025-05-22

申请号：US18826334

申请日：2024-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daesun Kim ,  Suklae Kim ,  Cheonbae Kim ,  Youngseok Park ,  Taejin Park ,  Hyunchul Yoon ,  Hyeonkyu Lee ,  Sungsoo Yim ,  Hyungeun Choi

IPC: H10B12/00 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Provided is a semiconductor device. The semiconductor device includes: a first connection region, a first memory block region, and a second connection region sequentially arranged; a first peripheral circuit region vertically overlapping with the first memory block region; first memory cells in the first memory block region; a first word line extending into the first and second connection regions by crossing the first memory block region, and electrically connected to the first memory cells; a first sub-word line driver in the first peripheral circuit region; and a first word line signal path electrically connecting the first word line and the first sub-word line driver. The first word line signal path includes at least one first routing contact coupled to the first word line in the first connection region, and at least one second routing contact coupled to the first word line in the second connection region.

公开(公告)号：US11462543B2

公开(公告)日：2022-10-04

申请号：US17320711

申请日：2021-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheonbae Kim ,  Seungjin Kim ,  Dongkyun Lee

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of lower electrodes arranged on a semiconductor substrate in a honeycomb structure; and a support connected to the plurality of lower electrodes and defining a plurality of open areas through which the plurality of lower electrodes are exposed. A center point of each of the plurality of open areas is arranged at a center point of a triangle formed by center points of three corresponding neighboring lower electrodes among the plurality of lower electrodes.

公开(公告)号：US20220115376A1

公开(公告)日：2022-04-14

申请号：US17320711

申请日：2021-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheonbae Kim ,  Seungjin Kim ,  Dongkyun Lee

IPC: H01L27/108 ,  H01L29/78 ,  H01L49/02

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of lower electrodes arranged on a semiconductor substrate in a honeycomb structure; and a support connected to the plurality of lower electrodes and defining a plurality of open areas through which the plurality of lower electrodes are exposed. A center point of each of the plurality of open areas is arranged at a center point of a triangle formed by center points of three corresponding neighboring lower electrodes among the plurality of lower electrodes.

公开(公告)号：US11818879B2

公开(公告)日：2023-11-14

申请号：US17901210

申请日：2022-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheonbae Kim ,  Seungjin Kim ,  Dongkyun Lee

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/78 ,  H10B12/00

CPC classification number: H10B12/30 ,  H01L28/60 ,  H01L29/7802

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of lower electrodes arranged on a semiconductor substrate in a honeycomb structure; and a support connected to the plurality of lower electrodes and defining a plurality of open areas through which the plurality of lower electrodes are exposed. A center point of each of the plurality of open areas is arranged at a center point of a triangle formed by center points of three corresponding neighboring lower electrodes among the plurality of lower electrodes.

公开(公告)号：US20250167107A1

公开(公告)日：2025-05-22

申请号：US18775049

申请日：2024-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun Choi ,  Taejin Park ,  Suklae Kim ,  Cheonbae Kim ,  Sungsoo Yim ,  Yoona Jang ,  Hyunyong Jeong

IPC: H01L23/522 ,  G11C5/06 ,  H01L23/528 ,  H10B12/00

Abstract: A semiconductor device is provided. The semiconductor device includes a first structure having a memory block region and an extension region; and a second structure having a peripheral circuit region. The first structure includes memory cells and a word line. The second structure includes a semiconductor body; a through-insulating pattern in the semiconductor body; and a peripheral transistor. The first and second structures include a word line signal path electrically connecting the word line to the peripheral transistor. The word line signal path includes a word line contact that is in contact with the word line in the extension region; a word line routing lower structure electrically connected to the word line contact and extending from the extension region into the memory block region; and a word line routing connection structure electrically connecting the word line routing lower structure to the word line routing peripheral structure.