公开(公告)号：US10079210B2

公开(公告)日：2018-09-18

申请号：US15186825

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do-sun Lee ,  Do-hyun Lee ,  Chul-sung Kim ,  Sang-jin Hyun ,  Joon-gon Lee

IPC: H01L21/02 ,  H01L23/535 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76876 ,  H01L23/485 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/785

Abstract: An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first direction, a gate line extending on the at least one fin-shaped active region in a second direction, the second direction intersecting with the first direction, a conductive region on a portion of the at least one fin-shaped active region at one side of the gate line, and a contact plug extending from the conductive region in a third direction, the third direction being perpendicular to a main plane of the substrate, may be provided. The contact plug may include a metal plug, a conductive barrier film on the conductive region, the conductive barrier film surrounding a sidewall and a bottom surface of the metal plug, the conductive barrier film including an N-rich metal nitride film, and a metal silicide film between the conductive region and the conductive barrier film.

公开(公告)号：US10262937B2

公开(公告)日：2019-04-16

申请号：US15679444

申请日：2017-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joon-gon Lee ,  Ryuji Tomita ,  Do-Sun Lee ,  Chul-sung Kim ,  Do-hyun Lee

IPC: H01L23/522 ,  H01L29/78 ,  H01L23/532 ,  H01L21/768

Abstract: An integrated circuit device includes at least one fin-type active region, a gate line on the at least one fin-type active region, and a source/drain region on the at least one fin-type active region at at least one side of the gate line. A first conductive plug is connected to the source/drain region and includes cobalt. A second conductive plug is connected to the gate line and spaced apart from the first conductive plug. A third conductive plug is connected to each of the first conductive plug and the second conductive plug. The third conductive plug electrically connects the first conductive plug and the second conductive plug.

公开(公告)号：US10164030B2

公开(公告)日：2018-12-25

申请号：US15604687

申请日：2017-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-bum Kim ,  Chul-sung Kim ,  Deok-han Bae ,  Bon-young Koo

IPC: H01L29/41 ,  H01L21/82 ,  H01L27/092 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238

Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.