公开(公告)号：US11037626B2

公开(公告)日：2021-06-15

申请号：US16432959

申请日：2019-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Jin Kim ,  Chung-Ho Yu ,  Yong-Kyu Lee ,  Jae-Yong Jeong

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  H01L27/115

Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

公开(公告)号：US09859848B2

公开(公告)日：2018-01-02

申请号：US14996248

申请日：2016-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyo-Soo Choo ,  Pil-Seon Yoo ,  Duk-Min Kwon ,  Chung-Ho Yu

IPC: G05F1/46 ,  H03F1/30 ,  G05F1/563 ,  G11C5/14 ,  G11C7/04 ,  G11C16/30 ,  G05F1/567 ,  G05F3/24 ,  G05F1/56

CPC classification number: H03F1/301 ,  G05F1/463 ,  G05F1/56 ,  G05F1/563 ,  G05F1/567 ,  G05F3/245 ,  G11C5/147 ,  G11C7/04 ,  G11C16/30 ,  H03F2200/447 ,  H03F2200/468

Abstract: A variable voltage generation circuit includes a first amplification circuit and a second amplification circuit. The first amplification circuit generates a first output voltage based on a reference voltage, a first feedback voltage, a temperature-varied voltage and a temperature-fixed voltage such that the first output voltage is varied in a first voltage range according to a variation of the operational temperature. The first amplification circuit generates the first feedback voltage based on the first output voltage. The second amplification circuit generates a second output voltage based on the first feedback voltage, a second feedback voltage, the temperature-varied voltage and the temperature-fixed voltage such that the second output voltage is varied in a second voltage range wider than the first voltage range according to the variation of the operational temperature. The second amplification circuit generates the second feedback voltage based on the second output voltage.

公开(公告)号：US11657858B2

公开(公告)日：2023-05-23

申请号：US17338097

申请日：2021-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Jin Kim ,  Chung-Ho Yu ,  Yong-Kyu Lee ,  Jae-Yong Jeong

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/1057 ,  G11C7/1084

Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

公开(公告)号：US20210295884A1

公开(公告)日：2021-09-23

申请号：US17338097

申请日：2021-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUN-JIN KIM ,  Chung-Ho Yu ,  Yong-Kyu Lee ,  Jae-Yong Jeong

IPC: G11C7/10

Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

公开(公告)号：US20200168277A1

公开(公告)日：2020-05-28

申请号：US16432959

申请日：2019-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Jin Kim ,  Chung-Ho Yu ,  Yong-Kyu Lee ,  Jae-Yong Jeong

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

公开(公告)号：US10395727B2

公开(公告)日：2019-08-27

申请号：US15922967

申请日：2018-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chung-Ho Yu ,  Dae-Seok Byeon ,  Jin-Bae Bang ,  Cheon-An Lee

IPC: G11C7/00 ,  G11C11/56 ,  G11C16/26 ,  G11C16/24 ,  G11C16/04

Abstract: A nonvolatile memory device includes multi-level cells. A sensing method of the nonvolatile memory device includes: precharging a bit line and a sense-out node during a first precharge interval; identifying a first state of a selected memory cell, by developing the sense-out node during a first develop time and sensing a first voltage level of the sense-out node; precharging the sense-out node to a second sense-out precharge voltage; and identifying the first state of the selected memory cell from a second state adjacent thereto, by developing the sense-out node during a second develop time different from the first develop time and sensing a second voltage level of the sense-out node.