公开(公告)号：US11729966B2

公开(公告)日：2023-08-15

申请号：US17723218

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo Kang ,  Wonseok Yoo ,  Hokyun An ,  Kyungwook Park ,  Dain Lee

IPC: H10B12/00 ,  G11C5/06 ,  H01L29/06

CPC classification number: H10B12/315 ,  G11C5/063 ,  H01L29/0649 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

公开(公告)号：US20210066200A1

公开(公告)日：2021-03-04

申请号：US16802676

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwook Park ,  Yoongoo Kang ,  Wonseok Yoo ,  Dain Lee

IPC: H01L23/532 ,  H01L27/108

Abstract: An integrated circuit device includes a conductive line formed on a substrate, an insulating spacer covering side walls of the conductive line and extending parallel with the conductive line, and a conductive plug that is spaced apart from the conductive line with the insulating spacer therebetween. The insulating spacer includes an insulating liner contacting the conductive line, an outer spacer contacting the conductive plug, and a barrier layer between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer.

公开(公告)号：US20230292491A1

公开(公告)日：2023-09-14

申请号：US18090043

申请日：2022-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwook Park ,  Sangmin Kang ,  Yoongoo Kang ,  Changwoo Seo ,  Suyoun Song ,  Dain Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/0335

Abstract: A semiconductor device may include contact plug structures on a substrate, and an insulation structure filling a space between the contact plug structures to insulate the contact plug structures from each other. The contact plug structures may be spaced apart from each other in a first direction. The insulation structure may include a first insulation pattern and a second insulation pattern. The second insulation pattern may include an insulation material having an etch selectivity with respect to silicon oxide. The first insulation pattern may contact a portion of sidewalls of the second insulation pattern and a portion of sidewalls of the contact plug structure. The first insulation pattern may include a material having a band gap higher than a band gap of the second insulation pattern.

公开(公告)号：US11177215B2

公开(公告)日：2021-11-16

申请号：US16802676

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwook Park ,  Yoongoo Kang ,  Wonseok Yoo ,  Dain Lee

IPC: H01L23/532 ,  H01L27/108

Abstract: An integrated circuit device includes a conductive line formed on a substrate, an insulating spacer covering side walls of the conductive line and extending parallel with the conductive line, and a conductive plug that is spaced apart from the conductive line with the insulating spacer therebetween. The insulating spacer includes an insulating liner contacting the conductive line, an outer spacer contacting the conductive plug, and a barrier layer between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer.

公开(公告)号：US12230498B2

公开(公告)日：2025-02-18

申请号：US17222195

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dain Lee ,  Yoongoo Kang ,  Wonseok Yoo ,  Jinwon Ma ,  Kyungwook Park ,  Changwoo Seo ,  Suyoun Song

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/36 ,  C23C16/455

Abstract: A semiconductor device manufacturing method includes loading a semiconductor substrate into a chamber, the semiconductor substrate including a silicon oxide film, depositing a seed layer on the silicon oxide film by supplying a first silicon source material, supplying a purge gas on the seed layer, depositing a protective layer on the seed layer by repeating a first cycle, the first cycle including supplying a base source material layer and subsequently supplying the first silicon source material, and depositing a silicon nitride film on the protective layer by repeating a second cycle, the second cycle including supplying a second silicon source material and subsequently supplying a nitrogen source material.

公开(公告)号：US11335689B2

公开(公告)日：2022-05-17

申请号：US16837274

申请日：2020-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo Kang ,  Wonseok Yoo ,  Hokyun An ,  Kyungwook Park ,  Dain Lee

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

公开(公告)号：US11037991B2

公开(公告)日：2021-06-15

申请号：US16392099

申请日：2019-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoongoo Kang ,  Changwoo Seo ,  Dain Lee ,  Wook-Yeol Yi ,  Hoi Sung Chung

IPC: H01L45/02 ,  H01L27/24 ,  H01L45/00

Abstract: A variable resistance memory device includes memory cells arranged on a substrate and an insulating structure between the memory cells. Each of the memory cells includes a variable resistance pattern and a switching pattern vertically stacked on the substrate. The insulating structure includes a first insulating pattern between the memory cells, and a second insulating pattern between the first insulating pattern and each of the memory cells. The first insulating pattern includes a material different from a material of the second insulating pattern.