公开(公告)号：US11335689B2

公开(公告)日：2022-05-17

申请号：US16837274

申请日：2020-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo Kang ,  Wonseok Yoo ,  Hokyun An ,  Kyungwook Park ,  Dain Lee

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

公开(公告)号：US11901421B2

公开(公告)日：2024-02-13

申请号：US17544158

申请日：2021-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hokyun An ,  Bumsoo Kim ,  Hyunseung Kim ,  Guangfan Jiao

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/3115 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/408 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/3115 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

Abstract: A semiconductor device may include a substrate, an interface insulation pattern, a gate insulation pattern, a threshold voltage controlling metal pattern and a conductive pattern. The interface insulation pattern may be formed on the substrate. The gate insulation pattern including an oxide having a dielectric constant higher than that of silicon oxide may be formed on the interface insulation pattern. The threshold voltage controlling metal pattern may be formed on the gate insulation pattern. The conductive pattern may be formed on the threshold voltage controlling metal pattern. First dopants including at least fluorine may be included within and at at least one surface of the gate insulation pattern and at an upper surface of an interface insulation pattern contacting the gate insulation pattern. The semiconductor device may have excellent electrical characteristics.

公开(公告)号：US11217669B2

公开(公告)日：2022-01-04

申请号：US16837408

申请日：2020-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hokyun An ,  Bumsoo Kim ,  Hyunseung Kim ,  Guangfan Jiao

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/3115 ,  H01L27/092

Abstract: A semiconductor device may include a substrate, an interface insulation pattern, a gate insulation pattern, a threshold voltage controlling metal pattern and a conductive pattern. The interface insulation pattern may be formed on the substrate. The gate insulation pattern including an oxide having a dielectric constant higher than that of silicon oxide may be formed on the interface insulation pattern. The threshold voltage controlling metal pattern may be formed on the gate insulation pattern. The conductive pattern may be formed on the threshold voltage controlling metal pattern. First dopants including at least fluorine may be included within and at at least one surface of the gate insulation pattern and at an upper surface of an interface insulation pattern contacting the gate insulation pattern. The semiconductor device may have excellent electrical characteristics.

公开(公告)号：US11729966B2

公开(公告)日：2023-08-15

申请号：US17723218

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo Kang ,  Wonseok Yoo ,  Hokyun An ,  Kyungwook Park ,  Dain Lee

IPC: H10B12/00 ,  G11C5/06 ,  H01L29/06

CPC classification number: H10B12/315 ,  G11C5/063 ,  H01L29/0649 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

公开(公告)号：US20220181326A1

公开(公告)日：2022-06-09

申请号：US17377932

申请日：2021-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hokyun An ,  Sungmi Yoon

IPC: H01L27/108

Abstract: Disclosed is a semiconductor memory device comprising a substrate with active patterns including first and second source/drain regions, a gate electrode extending across the active patterns in a first direction between the first and second source/drain regions, a line structure extending across the active patterns in a second direction that is transverse to the first direction and including a bit line electrically connected to the first source/drain region, a device isolation layer within a first trench which defines the active patterns, and contacts coupled to the second source/drain regions. The active pattern includes a first portion extending in a third direction parallel to a top surface of the substrate, and second and third portions connected to opposite ends of the first portion and vertically overlapping respective contacts. The second and third portions extend toward the respective contacts.