公开(公告)号：US12230498B2

公开(公告)日：2025-02-18

申请号：US17222195

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dain Lee ,  Yoongoo Kang ,  Wonseok Yoo ,  Jinwon Ma ,  Kyungwook Park ,  Changwoo Seo ,  Suyoun Song

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/36 ,  C23C16/455

Abstract: A semiconductor device manufacturing method includes loading a semiconductor substrate into a chamber, the semiconductor substrate including a silicon oxide film, depositing a seed layer on the silicon oxide film by supplying a first silicon source material, supplying a purge gas on the seed layer, depositing a protective layer on the seed layer by repeating a first cycle, the first cycle including supplying a base source material layer and subsequently supplying the first silicon source material, and depositing a silicon nitride film on the protective layer by repeating a second cycle, the second cycle including supplying a second silicon source material and subsequently supplying a nitrogen source material.

公开(公告)号：US11744073B2

公开(公告)日：2023-08-29

申请号：US17530915

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Kyungwook Park ,  Keun Lee ,  Hauk Han

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/40 ,  H01L29/423 ,  H01L21/67 ,  H01L21/285 ,  H01L21/3213 ,  C23C16/56 ,  C23C16/455 ,  C23C16/06 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

CPC classification number: H10B43/27 ,  C23C16/06 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/28568 ,  H01L21/32135 ,  H01L21/67069 ,  H01L29/40117 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/40 ,  H01L21/02636 ,  H01L21/67167 ,  H01L29/66545

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

公开(公告)号：US11335689B2

公开(公告)日：2022-05-17

申请号：US16837274

申请日：2020-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo Kang ,  Wonseok Yoo ,  Hokyun An ,  Kyungwook Park ,  Dain Lee

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

公开(公告)号：US20240306375A1

公开(公告)日：2024-09-12

申请号：US18444390

申请日：2024-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suyoun Song ,  Yoongoo Kang ,  Kyungwook Park ,  Youmin Ban ,  Changwoo Seo ,  Hyunchul Shim

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02

Abstract: An integrated circuit device includes a substrate having a plurality of active regions, a bit line extending in a horizontal direction on the substrate, an insulating capping pattern formed on the bit line and extending along the bit line, a direct contact disposed in a direct contact hole formed on the substrate and connected between a first active region selected from among the plurality of active regions and the bit line, and a spacer structure contacting a sidewall of the direct contact and a sidewall of the bit line The spacer structure includes a first spacer layer extending in a vertical direction on the sidewall of the direct contact and the sidewall of the bit line, and a second spacer layer covering at least a portion of the first spacer layer and extending in the vertical direction.

公开(公告)号：US11430665B2

公开(公告)日：2022-08-30

申请号：US16928548

申请日：2020-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Kyungwook Park ,  Wangyup Ryu ,  Keun Lee ,  Changwoo Lee ,  Hauk Han

IPC: C23C16/08 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/673 ,  C23C16/455

Abstract: A method of manufacturing a semiconductor device may include forming a stack structure by alternately stacking sacrificial layers and interlayer insulating layers on a substrate, forming channel structures extending through the stack structure, forming openings extending through the stack structure, forming lateral openings by removing the sacrificial layers exposed by the openings, and forming gate electrodes in the lateral openings. Forming the gate electrodes may include supplying a source gas containing tungsten (W) wherein the source gas is heated to a first temperature and is supplied in a deposition apparatus at the first temperature, supplying a reactant gas containing hydrogen (H) subsequently to supplying the source gas, wherein the reactant gas is heated to a second temperature and is supplied in the deposition apparatus at the second temperature, and supplying a purge gas subsequently to supplying the reactant gas.

公开(公告)号：US11189633B2

公开(公告)日：2021-11-30

申请号：US16700801

申请日：2019-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Kyungwook Park ,  Keun Lee ,  Hauk Han

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/67 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/285 ,  H01L21/3213 ,  C23C16/56 ,  C23C16/455 ,  C23C16/06 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

公开(公告)号：US20230292491A1

公开(公告)日：2023-09-14

申请号：US18090043

申请日：2022-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwook Park ,  Sangmin Kang ,  Yoongoo Kang ,  Changwoo Seo ,  Suyoun Song ,  Dain Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/0335

Abstract: A semiconductor device may include contact plug structures on a substrate, and an insulation structure filling a space between the contact plug structures to insulate the contact plug structures from each other. The contact plug structures may be spaced apart from each other in a first direction. The insulation structure may include a first insulation pattern and a second insulation pattern. The second insulation pattern may include an insulation material having an etch selectivity with respect to silicon oxide. The first insulation pattern may contact a portion of sidewalls of the second insulation pattern and a portion of sidewalls of the contact plug structure. The first insulation pattern may include a material having a band gap higher than a band gap of the second insulation pattern.

公开(公告)号：US20220077190A1

公开(公告)日：2022-03-10

申请号：US17530915

申请日：2021-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taisoo Lim ,  Kyungwook Park ,  Keun Lee ,  Hauk Han

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/67 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/285 ,  H01L21/3213 ,  C23C16/56 ,  C23C16/455 ,  C23C16/06 ,  H01L21/28

Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers that are alternately stacked on a substrate, channel structures spaced apart from each other in a first direction and extending vertically through the gate electrodes and the interlayer insulating layers to the substrate, and a first separation region extending vertically through the gate electrodes and the interlayer insulating layers. Each gate electrode includes a first conductive layer and a second conductive layer, the first conductive layer disposed between the second conductive layer and each of two adjacent interlayer insulating layers. In a first region, between an outermost channel structure and the first separation region, of each gate electrode, the first conductive layer has a decreasing thickness toward the first separation region and the second conductive layer has an increasing thickness toward the first separation region.

公开(公告)号：US11177215B2

公开(公告)日：2021-11-16

申请号：US16802676

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwook Park ,  Yoongoo Kang ,  Wonseok Yoo ,  Dain Lee

IPC: H01L23/532 ,  H01L27/108

Abstract: An integrated circuit device includes a conductive line formed on a substrate, an insulating spacer covering side walls of the conductive line and extending parallel with the conductive line, and a conductive plug that is spaced apart from the conductive line with the insulating spacer therebetween. The insulating spacer includes an insulating liner contacting the conductive line, an outer spacer contacting the conductive plug, and a barrier layer between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer.

公开(公告)号：US20240243183A1

公开(公告)日：2024-07-18

申请号：US18462724

申请日：2023-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin Kang ,  Sunggil Kim ,  Kyungwook Park

IPC: H01L29/45 ,  H01L23/00 ,  H01L29/417

CPC classification number: H01L29/456 ,  H01L24/08 ,  H01L29/41741 ,  H10B43/27

Abstract: A semiconductor device includes: a first substrate structure including a first substrate, circuit devices, and first bonding pads; and a second substrate structure connected to the first substrate structure. The second substrate structure includes: a source structure; gate electrodes stacked and spaced apart from each other below the source structure in a first direction; first contact plugs electrically connected to the gate electrodes and extending in the first direction; a second contact plug extending in the first direction in an external side of the gate electrodes and electrically connected to the source structure through an upper end; a diffusion barrier between the second contact plug and the source structure, wherein a level of a lower end thereof is higher than a level of an uppermost surface of the gate electrodes; and second bonding pads below the gate electrodes and connected to the first bonding pads.