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    DRAM device including an air gap and a sealing layer
    3.
    发明授权
    DRAM device including an air gap and a sealing layer 有权

    公开(公告)号：US11335689B2

    公开(公告)日：2022-05-17

    申请号：US16837274

    申请日：2020-04-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoongoo Kang ,  Wonseok Yoo ,  Hokyun An ,  Kyungwook Park ,  Dain Lee

    IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

    Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

    Integrated circuit device
    5.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US11177215B2

    公开(公告)日：2021-11-16

    申请号：US16802676

    申请日：2020-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungwook Park ,  Yoongoo Kang ,  Wonseok Yoo ,  Dain Lee

    IPC: H01L23/532 ,  H01L27/108

    Abstract: An integrated circuit device includes a conductive line formed on a substrate, an insulating spacer covering side walls of the conductive line and extending parallel with the conductive line, and a conductive plug that is spaced apart from the conductive line with the insulating spacer therebetween. The insulating spacer includes an insulating liner contacting the conductive line, an outer spacer contacting the conductive plug, and a barrier layer between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer.

    SEMICONDUCTOR DEVICE
    6.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230354587A1

    公开(公告)日：2023-11-02

    申请号：US18304930

    申请日：2023-04-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoongoo Kang ,  Sangyoon Oh ,  Wonseok Yoo ,  Kyeongock Chong ,  Haeseul Kang

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/02

    Abstract: A semiconductor device includes an active region; an isolation region on a side surface of the active region; a gate trench intersecting the active region and extending into the isolation region; a gate structure in the gate trench; a first impurity region and a second impurity region in the active region on both sides of the gate structure and spaced apart from each other; a bit line structure including a line portion intersecting the gate structure and a plug portion below the line portion and electrically connected to the first impurity region; and an insulating structure on a side surface of the plug portion. The insulating structure includes a spacer including a first material; an insulating pattern between the plug portion and the spacer and including a second material; and an insulating liner covering a side surface and a bottom surface of the insulating pattern and including a third material.

    DRAM device including an air gap and a sealing layer
    7.
    发明授权
    DRAM device including an air gap and a sealing layer 有权

    公开(公告)号：US11729966B2

    公开(公告)日：2023-08-15

    申请号：US17723218

    申请日：2022-04-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoongoo Kang ,  Wonseok Yoo ,  Hokyun An ,  Kyungwook Park ,  Dain Lee

    IPC: H10B12/00 ,  G11C5/06 ,  H01L29/06

    CPC classification number: H10B12/315 ,  G11C5/063 ,  H01L29/0649 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482

    Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

    INTEGRATED CIRCUIT DEVICE
    8.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20210066200A1

    公开(公告)日：2021-03-04

    申请号：US16802676

    申请日：2020-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungwook Park ,  Yoongoo Kang ,  Wonseok Yoo ,  Dain Lee

    IPC: H01L23/532 ,  H01L27/108

    Abstract: An integrated circuit device includes a conductive line formed on a substrate, an insulating spacer covering side walls of the conductive line and extending parallel with the conductive line, and a conductive plug that is spaced apart from the conductive line with the insulating spacer therebetween. The insulating spacer includes an insulating liner contacting the conductive line, an outer spacer contacting the conductive plug, and a barrier layer between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer.

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