公开(公告)号：US20180366554A1

公开(公告)日：2018-12-20

申请号：US15871055

申请日：2018-01-14

申请人： Samsung Electronics Co., Ltd.

发明人： Eun Yeoung CHOI ,  Jun Kyu YANG ,  Young Jin NOH ,  Jae Young AHN ,  Jae Hyun YANG ,  Dong Chul YOO ,  Jae Ho CHOI

IPC分类号： H01L29/51 ,  H01L27/11582 ,  H01L27/11565

CPC分类号： H01L29/513 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

摘要： A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.