公开(公告)号：US20180366554A1

公开(公告)日：2018-12-20

申请号：US15871055

申请日：2018-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung CHOI ,  Jun Kyu YANG ,  Young Jin NOH ,  Jae Young AHN ,  Jae Hyun YANG ,  Dong Chul YOO ,  Jae Ho CHOI

IPC: H01L29/51 ,  H01L27/11582 ,  H01L27/11565

CPC classification number: H01L29/513 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.

公开(公告)号：US20220028889A1

公开(公告)日：2022-01-27

申请号：US17495614

申请日：2021-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Yeoung CHOI ,  Hyung Joon KIM ,  Su Hyeong LEE ,  Jung Geun JEE

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/16 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28

Abstract: A vertical-type memory device includes a plurality of gate electrodes stacked on a substrate; and a vertical channel structure penetrating through the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate. The vertical channel structure includes a channel extending in the first direction, a first filling film that partially fills an internal space of the channel, a first liner on at least a portion of an upper surface of the first filling film and an upper internal side wall of the channel extending beyond the first filling film away from the substrate. The first liner includes n-type impurities. The vertical channel structure includes a second filling film on at least a portion of the first liner, and a pad on the second filling film and in contact with the first liner.

公开(公告)号：US20200381446A1

公开(公告)日：2020-12-03

申请号：US16582240

申请日：2019-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung CHOI ,  Hyung Joon Kim ,  Su Hyeong Lee ,  Yong Seok Cho

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode on the plurality of first gate electrodes, a first channel structure extending through the plurality of first gate electrodes and a portion of the second gate electrode, a buried insulation pattern on a sidewall of the first channel structure, of which an upper surface is at a higher level than a top end of the first channel structure, a second channel structure extending through a remainder of the second gate electrode, the second channel structure connected to the first channel structure, and a buried conductive pattern on a sidewall of the second channel structure.

公开(公告)号：US20220093642A1

公开(公告)日：2022-03-24

申请号：US17540688

申请日：2021-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung CHOI ,  Hyung Joon KIM ,  Su Hyeong LEE ,  Yong Seok CHO

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode on the plurality of first gate electrodes, a first channel structure extending through the plurality of first gate electrodes and a portion of the second gate electrode, a buried insulation pattern on a sidewall of the first channel structure, of which an upper surface is at a higher level than a top end of the first channel structure, a second channel structure extending through a remainder of the second gate electrode, the second channel structure connected to the first channel structure, and a buried conductive pattern on a sidewall of the second channel structure.