公开(公告)号：US20220376046A1

公开(公告)日：2022-11-24

申请号：US17648155

申请日：2022-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol Kim ,  Jeong Yeon Seo ,  Dong Kwon Kim ,  Hyun Ho Jung

IPC: H01L29/06

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first active pattern, which extends in a first direction on the substrate, a second active pattern, which extends in the first direction on the substrate and is spaced apart from the first active pattern by a first pitch in a second direction different from the first horizontal direction, a third active pattern, which extends in the first direction on the substrate and is spaced apart from the second active pattern by a second pitch greater than the first pitch in the second direction, a field insulating layer, which borders side walls of each of the first to third active patterns, a dam, which is between the first active pattern and the second active pattern on the field insulating layer, the region between the second active pattern and the third active pattern being free of the dam, a gate electrode, which extends in the second direction, and has a first portion on the first active pattern, a second portion on the second active pattern, and a third portion on the third active pattern, a first work function layer between the first portion of the gate electrode and the dam, and a second work function layer between the second portion of the gate electrode and the dam.

公开(公告)号：US20160365425A1

公开(公告)日：2016-12-15

申请号：US14739662

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd. ,  Globalfoundries Inc.

Inventor： Hsueh-Chung Chen ,  Su Chen Fan ,  Dong Kwon Kim ,  Sean Lian ,  Fee Li Lie ,  Linus Jang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L29/6653 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/3086 ,  H01L21/31116

Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.

Abstract translation: 本发明的一个方面包括具有用于侧壁图像转印过程的亚光刻尺寸的独立间隔物。 独立间隔件包括：第一间隔层，其具有设置在半导体层上的第一部分; 以及第二间隔层，其具有设置在第一间隔层的第一部分上的第一表面，其中第一间隔层具有第一介电常数，第二间隔层具有第二介电常数，第一介电常数大于第二间隔层 介电常数，并且其中第一和第二间隔层中的每一个的尺寸共同确定独立间隔物的亚光刻横向尺寸。

公开(公告)号：US12068242B2

公开(公告)日：2024-08-20

申请号：US17373900

申请日：2021-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Dong Kwon Kim ,  Jinwook Lee ,  Jongchul Park ,  Wonhyuk Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device including a gate pattern on a substrate and including a gate dielectric layer, a gate electrode, and a gate capping pattern that are sequentially stacked; a gate spacer on a sidewall of the gate pattern; a source/drain pattern in the substrate; a contact pad on the source/drain pattern, a source/drain contact on the contact pad; and a buried dielectric pattern between the gate spacer and the source/drain contact, wherein the gate spacer includes a first segment between the gate electrode and the source/drain pattern; a second segment that extends from the first segment and between the gate electrode and the source/drain contact; and a third segment on the second segment, the buried dielectric pattern is between the third segment and the source/drain contact, and is absent between the first segment and the contact pad and is absent between the second segment and the source/drain contact.

公开(公告)号：US11869938B2

公开(公告)日：2024-01-09

申请号：US17516192

申请日：2021-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae Geon Jung ,  Dong Kwon Kim ,  Cheol Kim

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/0665 ,  H01L29/0847 ,  H01L29/4236

Abstract: A semiconductor device includes a substrate, a first active pattern that includes a first side wall and a second side wall opposite to the first side wall in a second horizontal direction, a first insulating structure in a first trench extending in the first horizontal direction on the first side wall of the first active pattern, a second insulating structure in a second trench extending in the first horizontal direction on the second side of the first active pattern, and includes a first insulating layer on side walls and a bottom surface of the second trench, and a second insulating layer in the second trench on the first insulating layer, a gate-cut extending in the first horizontal direction on the first insulating structure, and a gate electrode extending in the second horizontal direction on the first active pattern.

公开(公告)号：US20230031542A1

公开(公告)日：2023-02-02

申请号：US17716278

申请日：2022-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Ho Jung ,  Dong Kwon Kim ,  Cheol Kim

IPC: H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes: a substrate; an active pattern and a field insulating layer surrounding a sidewall of the active pattern on the substrate; first and second gate electrodes on the active pattern and extending in a direction different from that of the active pattern; an interlayer insulating layer surrounding a sidewall of each of the first and second gate electrodes; a gate spacer on opposing sidewalls of each of the first and second gate electrodes that includes a first sidewall and a second sidewall opposite the first sidewall in the first horizontal direction, each of which contacts the interlayer insulating layer; and a first gate cut dividing the second gate electrode into two portions, wherein the first gate cut includes a same material as the gate spacer; and wherein a first width of the first gate cut is smaller than a second width of the gate spacer.

公开(公告)号：US09653571B2

公开(公告)日：2017-05-16

申请号：US14739662

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd. ,  GLOBALFOUNDRIES Inc.

Inventor： Hsueh-Chung Chen ,  Su Chen Fan ,  Dong Kwon Kim ,  Sean Lian ,  Fee Li Lie ,  Linus Jang

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L29/6653 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/3086 ,  H01L21/31116

Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.