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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240371717A1

    公开(公告)日：2024-11-07

    申请号：US18409221

    申请日：2024-01-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donggon Yoo ,  Sunjung Lee ,  Jeongwon Hwang ,  Myung-Ho Kong ,  Yongho Ha

    IPC: H01L23/31 ,  H01L23/29 ,  H01L23/528 ,  H01L23/532

    Abstract: A semiconductor device includes a mold layer defining a trench and a conductive structure disposed on the trench. The conductive structure includes a conductive layer and a liner, and the conductive layer includes upper and lower portions. The liner includes a base portion and a sidewall portion on the base portion, and the upper portion of the conductive layer is disposed at a level higher than the sidewall portion of the liner. The sidewall portion of the liner is interposed between the lower portion of the conductive layer and the mold layer, and a top surface of the base portion of the liner is in contact with a bottom surface of the lower portion of the conductive layer. A width of the sidewall portion of the liner may decrease as a level increases.

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11374001B2

    公开(公告)日：2022-06-28

    申请号：US16851476

    申请日：2020-04-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunyoung Noh ,  Wandon Kim ,  Hyunbae Lee ,  Donggon Yoo ,  Dong-Chan Lim

    IPC: H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535

    Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250022930A1

    公开(公告)日：2025-01-16

    申请号：US18754608

    申请日：2024-06-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunjung Lee ,  Donggon Yoo ,  Jeongwon Hwang

    IPC: H01L29/423 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including semiconductor patterns vertically stacked to be spaced apart from each other, a gate electrode on the plurality of semiconductor patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the gate contact, the first metal layer including a first conductive via and a first interconnection pattern on the first conductive via, a second metal layer on the first metal layer, the second metal layer including a second conductive via and a second interconnection pattern on the second conductive via, and a diffusion prevention pattern between the first interconnection pattern and the second conductive via. A level of a bottom surface of the diffusion prevention pattern may be lower than a level of the topmost surface of the first interconnection pattern.

    SEMICONDUCTOR DEVICE
    5.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240120392A1

    公开(公告)日：2024-04-11

    申请号：US18244257

    申请日：2023-09-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunjung Lee ,  Donggon Yoo ,  Jeongwon Hwang ,  Sukhoon Kim

    IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

    Abstract: A semiconductor device includes a substrate including active regions extending in a first direction; a device isolation layer surrounding the active regions on the substrate; gate structures intersecting the active regions and extending on the substrate in a second direction; source/drain regions on the active regions; contact plugs connected to the source/drain regions, respectively; a vertical buried structure penetrating through at least a portion of the device isolation layer, and in contact with the contact plugs; a vertical insulating layer covering at least a portion of side surfaces of the vertical buried structure; a horizontal buried structure below the vertical buried structure; a first conductive barrier covering at least a portion of an upper surface and side surfaces of the horizontal buried structure; and a metal-semiconductor compound pattern between the vertical buried structure and the first conductive barrier, wherein the vertical buried structure is between source/drain regions.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    6.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20230253310A1

    公开(公告)日：2023-08-10

    申请号：US18299926

    申请日：2023-04-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eui Bok LEE ,  Donggon Yoo ,  Wandon Kim

    IPC: H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L23/528

    CPC classification number: H01L23/5226 ,  H01L29/0649 ,  H01L29/0847 ,  H01L23/5283

    Abstract: A semiconductor device including transistors on a substrate, a first interlayer insulating layer on the transistors, a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer, a dielectric layer being selectively on a top surface of the first interlayer insulating layer except top surfaces of the first and second lower interconnection lines, an etch stop layer on the first and second lower interconnection lines and the dielectric layer, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer may be provided.

    Semiconductor device and method of fabricating the same
    7.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US12218046B2

    公开(公告)日：2025-02-04

    申请号：US18299926

    申请日：2023-04-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eui Bok Lee ,  Donggon Yoo ,  Wandon Kim

    IPC: H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08

    Abstract: A semiconductor device including transistors on a substrate, a first interlayer insulating layer on the transistors, a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer, a dielectric layer being selectively on a top surface of the first interlayer insulating layer except top surfaces of the first and second lower interconnection lines, an etch stop layer on the first and second lower interconnection lines and the dielectric layer, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer may be provided.

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    8.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20250022875A1

    公开(公告)日：2025-01-16

    申请号：US18615943

    申请日：2024-03-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sunjung Lee ,  Donggon Yoo ,  Jeongwon Hwang

    IPC: H01L27/06 ,  H01L23/522 ,  H01L27/02 ,  H01L27/092

    Abstract: The present disclosure relates to three-dimensional semiconductor devices. An example three-dimensional semiconductor device includes a back-side metal layer, a lower active region on the back-side metal layer, the lower active region including a lower channel pattern and a lower source drain pattern connected with the lower channel pattern, an upper active region on the lower active region, the upper active region including an upper channel pattern and an upper source drain pattern connected with the upper channel pattern, an interlayer insulating layer enclosing the lower and upper source drain patterns, a penetration conductive pattern extending through the interlayer insulating layer in a vertical direction, and an inhibitor covering a side surface of a lower portion of the penetration conductive pattern. The inhibitor includes a carbon atom.

    INTEGRATED CIRCUIT DEVICE
    9.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20240429303A1

    公开(公告)日：2024-12-26

    申请号：US18658176

    申请日：2024-05-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Donggon Yoo ,  Eunhyea Ko ,  Sunjung Lee ,  Yongho Ha ,  Jeongwon Hwang

    IPC: H01L29/45 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

    Abstract: An integrated circuit device includes a substrate, a fin-type active region extending in a first horizontal direction on a first surface of the substrate, a source/drain region on the fin-type active region, an active contact on the source/drain region and electrically connected to the source/drain region, a wiring line extending at a vertical level higher than the source/drain region, a via contact penetrating an insulating layer on the source/drain region and serving as a medium of electrical connection between the active contact and the wiring line, and an adhesive layer between the wiring line and the insulating layer and contacting the wiring line, wherein the via contact includes a top via contact and a bottom via contact, the top via contact includes a metal different from a metal included in the bottom via contact, and the wiring line and the top via contact are in direct contact with each other.

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