公开(公告)号：US20180331201A1

公开(公告)日：2018-11-15

申请号：US16026749

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L27/092 ,  H01L21/762 ,  H01L21/3205 ,  H01L29/51

CPC classification number: H01L29/6681 ,  H01L21/02255 ,  H01L21/32053 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.

公开(公告)号：US20130224936A1

公开(公告)日：2013-08-29

申请号：US13690394

申请日：2012-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwook Lee ,  Donggu Yi

IPC: H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/823821

Abstract: Methods of manufacturing a semiconductor device are provided. The method includes constructing and arranging a semiconductor substrate to include a first active region and a second active region and forming mold patterns on the semiconductor substrate. The mold patterns have openings that expose a top surface of the semiconductor substrate. A plurality of first semiconductor fins are formed in openings at the first active region and a plurality of second semiconductor fins in openings at the second active region and selectively recessing top surfaces of the mold patterns. A recessed depth of the mold patterns on the first active region is different than a recessed depth of the mold patterns on the second active region. A gate electrode is formed over the first and second semiconductor fins. A distance between a first semiconductor fin of the plurality of first semiconductor fins and a second semiconductor fin of the plurality of second semiconductor fins adjacent the first semiconductor fin is greater than a distance between two or more first semiconductor fins of the plurality of first semiconductor fins that are adjacent each other.

Abstract translation: 提供制造半导体器件的方法。 该方法包括构造和布置半导体衬底以包括第一有源区和第二有源区，并在半导体衬底上形成模型图案。 模具图案具有露出半导体衬底的顶表面的开口。 多个第一半导体散热片形成在第一有源区域的开口中，多个第二半导体鳍片在第二有源区域的开口中形成，并且选择性地凹陷模具图案的顶表面。 第一主动区域上的模具图案的凹陷深度不同于第二活动区域上的模具图案的凹陷深度。 栅电极形成在第一和第二半导体鳍上。 多个第一半导体鳍片的第一半导体鳍片与邻近第一半导体鳍片的多个第二半导体鳍片的第二半导体鳍片之间的距离大于多个第一半导体鳍片的两个或更多个第一半导体鳍片之间的距离 彼此相邻。