公开(公告)号：US11816563B2

公开(公告)日：2023-11-14

申请号：US16409487

申请日：2019-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Engin Ipek

IPC: G06F11/07 ,  G06F11/10 ,  G06N3/08 ,  G06F17/16

CPC classification number: G06N3/08 ,  G06F17/16

Abstract: A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.

公开(公告)号：US20200234114A1

公开(公告)日：2020-07-23

申请号：US16409487

申请日：2019-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Engin Ipek

IPC: G06N3/08 ,  G06F17/16

Abstract: A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.

公开(公告)号：US09256369B2

公开(公告)日：2016-02-09

申请号：US13865959

申请日：2013-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  University of Rochester

Inventor： Mahdi Nazm Bojnordi ,  Engin Ipek ,  Arun S. Jagatheesan

IPC: G06F13/14 ,  G06F3/06 ,  G11C7/10 ,  G06F13/16

CPC classification number: G06F3/0611 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1668 ,  G11C7/1072

Abstract: One embodiment includes a programmable memory controller. The programmable memory controller includes a request processor that comprises a first domain-specific instruction set architecture (ISA) for accelerating common requests. A transaction processor comprises a second domain-specific ISA for accelerating transaction processing tasks. A dedicated command logic module inspects each memory command to a memory device and stalls particular commands for meeting timing constraints for application specific control of the memory device.

Abstract translation: 一个实施例包括可编程存储器控制器。 可编程存储器控制器包括请求处理器，该请求处理器包括用于加速公共请求的第一特定于域的指令集体系结构（ISA）。 交易处理器包括用于加速事务处理任务的第二域专用ISA。 专用命令逻辑模块将每个存储器命令检查到存储器设备，并且停止特定的命令以满足对存储器设备的专用控制的时序约束。

公开(公告)号：US20130282972A1

公开(公告)日：2013-10-24

申请号：US13865959

申请日：2013-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  UNIVERSITY OF ROCHESTER

Inventor： Mahdi Nazm Bojnordi ,  Engin Ipek ,  Arun S. Jagatheesan

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F3/0611 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1668 ,  G11C7/1072

Abstract: One embodiment includes a programmable memory controller. The programmable memory controller includes a request processor that comprises a first domain-specific instruction set architecture (ISA) for accelerating common requests. A transaction processor comprises a second domain-specific ISA for accelerating transaction processing tasks. A dedicated command logic module inspects each memory command to a memory device and stalls particular commands for meeting timing constraints for application specific control of the memory device.

Abstract translation: 一个实施例包括可编程存储器控制器。 可编程存储器控制器包括请求处理器，该请求处理器包括用于加速公共请求的第一特定于域的指令集体系结构（ISA）。 交易处理器包括用于加速事务处理任务的第二域专用ISA。 专用命令逻辑模块将每个存储器命令检查到存储器设备，并且停止特定的命令以满足对存储器设备的专用控制的时序约束。