公开(公告)号：US20190237382A1

公开(公告)日：2019-08-01

申请号：US16148471

申请日：2018-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Choon KIM ,  Woo Hyun PARK ,  Eon Soo JANG ,  Young Sang CHO

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L23/367 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.

公开(公告)号：US20190057918A1

公开(公告)日：2019-02-21

申请号：US15922478

申请日：2018-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Hyun PARK ,  Jae Choon KIM

IPC: H01L23/31 ,  H01L27/146 ,  H01L25/065 ,  H01L23/532 ,  H01L23/528 ,  H01L23/34 ,  H01L21/768 ,  H04N5/225

CPC classification number: H01L23/3114 ,  H01L21/76877 ,  H01L23/345 ,  H01L23/5283 ,  H01L23/5329 ,  H01L25/0657 ,  H01L27/14603 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H04N5/2253

Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.