公开(公告)号：US20200212979A1

公开(公告)日：2020-07-02

申请号：US16727391

申请日：2019-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seijoon SHIM ,  Joonho CHO ,  Hayoung YANG ,  Eunae LEE ,  Taejun JANG ,  Jonghwan KIM

IPC: H04B7/06 ,  H04L5/00 ,  H04B7/0417 ,  H04B7/08 ,  H04L27/26

Abstract: A base station for transmitting and receiving signals in a wireless communication system is provided. The base station includes a transceiver, and at least one processor configured to obtain reception antenna weights for the base station including an array of a plurality of antennas, and transmission antenna weights for at least one user equipment (UE), convert signals received from the at least one UE through a plurality of reception paths, into beam-domain signals, based on the transmission antenna weights and the reception antenna weights, combine the converted beam-domain signals by applying predefined combining weights to the converted beam-domain signals, and obtain data from the combined signals.

公开(公告)号：US20230141789A1

公开(公告)日：2023-05-11

申请号：US17864736

申请日：2022-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Eunae LEE ,  Byeonggyu PARK ,  Yeonggeol SONG

IPC: G11C11/406 ,  G11C11/4093

CPC classification number: G11C11/40615 ,  G11C11/4093 ,  G11C11/40618

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

公开(公告)号：US20240249793A1

公开(公告)日：2024-07-25

申请号：US18394627

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin YOU ,  Eunae LEE ,  Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Kyomin SOHN

IPC: G11C29/52 ,  G11C11/406 ,  G11C11/408

CPC classification number: G11C29/52 ,  G11C11/40615 ,  G11C11/4085

Abstract: A memory controller manages a refresh. The memory controller is configured to communicate with a memory device including a memory cell array that include of a plurality of word lines may include a scheduler configured to control commands provided to the plurality of word lines, an error correction code engine that has a register including N entries and is configured to store, in the register, a first parameter which includes address information and active number information of N word lines among the plurality of word lines based on counting the number of actives of the plurality of word lines, a comparator configured to compare the first parameter with a threshold parameter, and a refresh management (RFM) decision circuit configured to determine refresh frequency of the plurality of word lines based on results output from the comparator and to generate an RFM command.

公开(公告)号：US20220122685A1

公开(公告)日：2022-04-21

申请号：US17313236

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggi AHN ,  Yesin RYU ,  Jun Jin KONG ,  Eunae LEE ,  Jihyun CHOI

IPC: G11C29/42 ,  G11C29/46 ,  G11C29/14 ,  G11C29/52

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.