公开(公告)号：US11664346B2

公开(公告)日：2023-05-30

申请号：US17306625

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunkyoung Choi

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1815 ,  H01L2924/3512

Abstract: A semiconductor package includes semiconductor chips on a package substrate, and a dummy pad disposed between and the semiconductor chips and overlapping at least a portion of the semiconductor chips. The dummy pad being disposed on the package substrate and in a space between the package substrate and the semiconductor chips.

公开(公告)号：US12027471B2

公开(公告)日：2024-07-02

申请号：US17576113

申请日：2022-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyoung Choi

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/68 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/0652 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2225/06589

Abstract: A semiconductor package including a package base substrate, an interposer on the package base substrate, a plurality of semiconductor chips on the interposer, and a stiffener structure including a stiffener frame and a stiffener extension portion, the stiffener frame being on the package base substrate and apart from the interposer, the stiffener extension portion extending from the stiffener frame, spaced apart from the plurality of semiconductor chips, and extending onto the interposer to have a portion on the interposer, and the stiffener frame being an integral structure with the extension portion, may be provided.

公开(公告)号：US11776918B2

公开(公告)日：2023-10-03

申请号：US17705770

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyoung Choi ,  Suchang Lee ,  Yunseok Choi

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/49838 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.

公开(公告)号：US11557543B2

公开(公告)日：2023-01-17

申请号：US17208798

申请日：2021-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunkyoung Choi

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/10

Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface, and including a first active layer on a portion adjacent to the first surface; a first redistribution structure on the first surface of the first semiconductor chip, wherein the first redistribution structure includes a first area and a second area next to the first area; a second semiconductor chip mounted in the first area of the first redistribution structure, including a third surface, which faces the first surface, and a fourth surface, and including a second active layer on a portion adjacent to the third surface; a conductive post mounted in the second area of the first redistribution structure; a molding layer at least partially surrounding the second semiconductor chip and the conductive post on the first redistribution structure; and a second redistribution structure disposed on the molding layer and connected to the conductive post.

公开(公告)号：US11315886B2

公开(公告)日：2022-04-26

申请号：US16848106

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyoung Choi ,  Suchang Lee ,  Yunseok Choi

IPC: H01L23/16 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.

公开(公告)号：US20230411355A1

公开(公告)日：2023-12-21

申请号：US18138564

申请日：2023-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoe Cho ,  Eunkyoung Choi ,  Changeun Joo

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L2225/06513 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3107 ,  H01L23/3135 ,  H01L24/17 ,  H01L25/0652 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/17181 ,  H01L2225/06568 ,  H01L23/481

Abstract: A semiconductor package includes a first semiconductor chip including a first interconnection structure on first surface, through-electrodes connected to the first interconnection structure, a redistribution structure on a second surface and connected to the through-electrodes, and first contact pads on the redistribution structure, a second semiconductor chip including a second interconnection structure, the second semiconductor chip having a first region on which the first semiconductor chip is disposed, and second contact pads on the first region and bonded to the first contact pads, first conductive posts on the first interconnection structure, a first mold layer on the first interconnection structure and surrounding the first conductive posts, second conductive posts on the second region, a second mold layer on the second region and surrounding the second conductive posts, the first semiconductor chip, and the first molded layer, and a passivation layer on the first molded layer and the second molded layer.

公开(公告)号：US20230066895A1

公开(公告)日：2023-03-02

申请号：US17856122

申请日：2022-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yukyung Park ,  Hyunjung Song ,  Eunkyoung Choi

IPC: H01F17/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/498 ,  H01L21/56

Abstract: An inductor includes a semiconductor substrate provided with a plurality of wiring levels including a first wiring level and a second wiring level, a straight conductive line, at the first wiring level of the semiconductor substrate, having a first end, a conductive coil of a spiral pattern, at the second wiring level over the first wiring level, having a second end, and a conductive via vertically connecting the first end of the straight conductive line to the second end of the conductive coil. When viewed in a plan view, a plurality of dummy patterns are arranged in a first area defined by an innermost turn of the spiral pattern.