公开(公告)号：US11328966B2

公开(公告)日：2022-05-10

申请号：US16749620

申请日：2020-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun Kim ,  Yonghoe Cho ,  Sunkyoung Seo ,  Seunghoon Yeon ,  Sanguk Han

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  G01R31/28 ,  G01R27/26

Abstract: A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

公开(公告)号：US11862596B2

公开(公告)日：2024-01-02

申请号：US18094794

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namhoon Kim ,  Seunghoon Yeon ,  Yonghoe Cho

IPC: H01L23/00

CPC classification number: H01L24/20 ,  H01L24/13 ,  H01L2224/2101 ,  H01L2224/214

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, a semiconductor chip on the redistribution substrate and including a chip pad electrically connected to the redistribution substrate, and a conductive terminal on the redistribution substrate. The redistribution substrate includes a first dielectric layer, a first redistribution pattern, a second dielectric layer, a second redistribution pattern, and a first insulative pattern. The first redistribution pattern electrically connects the chip pad and the second redistribution pattern. The first insulative pattern has a first surface in contact with the first redistribution pattern and a second surface in contact with the second redistribution pattern. The second surface is opposite to the first surface. A width at the first surface of the first insulative pattern is the same as or greater than a width at the second surface of the first insulative pattern.

公开(公告)号：US11776941B2

公开(公告)日：2023-10-03

申请号：US17357378

申请日：2021-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoe Cho ,  Sunkyoung Seo ,  Chajea Jo

IPC: H01L23/498 ,  H01L25/16 ,  H01L23/14 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/167 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a package substrate, a connection substrate on the package substrate, a first image sensor chip on the connection substrate, a second image sensor chip on the connection substrate, the second image sensor chip being horizontally spaced apart from the first image sensor chip, and a memory chip disposed on the package substrate and electrically connected to the first image sensor chip through the connection substrate. A distance between the first image sensor chip and the second image sensor chip is less than a thickness of the first image sensor chip.

公开(公告)号：US11244894B2

公开(公告)日：2022-02-08

申请号：US16809116

申请日：2020-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghoon Yeon ,  Wonil Lee ,  Yonghoe Cho

IPC: H01L29/00 ,  H01L23/522 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor device having a through silicon via, a lower redistribution structure on the semiconductor device, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the through silicon via, a package connection terminal on the lower redistribution structure and electrically connected to the lower redistribution pattern, an upper redistribution structure on the semiconductor device and including an upper redistribution insulating layer and an upper redistribution pattern electrically connected to the through silicon via, a conductive via in contact with the upper redistribution pattern and on the upper redistribution insulating layer, a connection pad on the conductive via, and a passive element pattern on the upper redistribution structure and electrically connected to the conductive via.

公开(公告)号：US10748953B2

公开(公告)日：2020-08-18

申请号：US16803041

申请日：2020-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghoe Cho ,  Jongbo Shim ,  Seunghoon Yeon ,  Won Il Lee

IPC: H01L21/00 ,  H01L27/146

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a top surface, on which has been formed a color filter and a micro-lens, and a bottom surface opposite to the top surface, forming a redistribution line on the bottom surface of the semiconductor substrate, and forming on the bottom surface of the semiconductor substrate a passivation layer covering the redistribution line. After the redistribution line and passivation layer are formed, an oxide layer between the redistribution line and the passivation is formed at a temperature that avoids thermal damage to the color filter and the micro-lens.

公开(公告)号：US11869818B2

公开(公告)日：2024-01-09

申请号：US17733411

申请日：2022-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun Kim ,  Yonghoe Cho ,  Sunkyoung Seo ,  Seunghoon Yeon ,  Sanguk Han

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  G01R31/28 ,  G01R27/26

CPC classification number: H01L22/32 ,  G01R27/2605 ,  G01R31/2818 ,  H01L22/14 ,  H01L23/3128 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513

Abstract: A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

公开(公告)号：US20230411355A1

公开(公告)日：2023-12-21

申请号：US18138564

申请日：2023-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoe Cho ,  Eunkyoung Choi ,  Changeun Joo

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L2225/06513 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3107 ,  H01L23/3135 ,  H01L24/17 ,  H01L25/0652 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/17181 ,  H01L2225/06568 ,  H01L23/481

Abstract: A semiconductor package includes a first semiconductor chip including a first interconnection structure on first surface, through-electrodes connected to the first interconnection structure, a redistribution structure on a second surface and connected to the through-electrodes, and first contact pads on the redistribution structure, a second semiconductor chip including a second interconnection structure, the second semiconductor chip having a first region on which the first semiconductor chip is disposed, and second contact pads on the first region and bonded to the first contact pads, first conductive posts on the first interconnection structure, a first mold layer on the first interconnection structure and surrounding the first conductive posts, second conductive posts on the second region, a second mold layer on the second region and surrounding the second conductive posts, the first semiconductor chip, and the first molded layer, and a passivation layer on the first molded layer and the second molded layer.

公开(公告)号：US11824076B2

公开(公告)日：2023-11-21

申请号：US17731022

申请日：2022-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoe Cho ,  Chungsun Lee ,  Yoonha Jung ,  Chajea Jo

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/48 ,  H01L21/683

CPC classification number: H01L27/14634 ,  H01L21/6835 ,  H01L23/481 ,  H01L24/32 ,  H01L27/1469 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14636 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/32225 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip.

公开(公告)号：US11552037B2

公开(公告)日：2023-01-10

申请号：US17193435

申请日：2021-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namhoon Kim ,  Seunghoon Yeon ,  Yonghoe Cho

IPC: H01L23/00

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate, a semiconductor chip on the redistribution substrate and including a chip pad electrically connected to the redistribution substrate, and a conductive terminal on the redistribution substrate. The redistribution substrate includes a first dielectric layer, a first redistribution pattern, a second dielectric layer, a second redistribution pattern, and a first insulative pattern. The first redistribution pattern electrically connects the chip pad and the second redistribution pattern. The first insulative pattern has a first surface in contact with the first redistribution pattern and a second surface in contact with the second redistribution pattern. The second surface is opposite to the first surface. A width at the first surface of the first insulative pattern is the same as or greater than a width at the second surface of the first insulative pattern.

公开(公告)号：US11335719B2

公开(公告)日：2022-05-17

申请号：US16802683

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoe Cho ,  Chungsun Lee ,  Yoonha Jung ,  Chajea Jo

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/48 ,  H01L21/683

Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip.