公开(公告)号：US20240072060A1

公开(公告)日：2024-02-29

申请号：US18499258

申请日：2023-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  SEUNGHYUN SONG ,  KI-IL KIM ,  GUNHO JO ,  KANG-ILL SEO

IPC: H01L27/12 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088

CPC classification number: H01L27/1203 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/088

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

公开(公告)号：US20230352408A1

公开(公告)日：2023-11-02

申请号：US17936106

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNGHOON JUNG ,  WONHYUK HONG ,  INCHAN HWANG ,  GUNHO JO ,  KANG-ILL SEO

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/66439

Abstract: Methods of forming an integrated circuit devices may include providing first and second active regions, an isolation layer, and first and second sacrificial stack structures. The first and second sacrificial stack structures may contact the first and second active regions, and the first and second sacrificial stack structures may each include a channel layer and a sacrificial layer. The methods may also include forming an etch stop layer on the isolation layer, replacing portions of the first and second sacrificial stack structures with first and second source/drain regions, forming a front contact including a front contact plug, forming a back-side insulator, and forming a back contact plug in the isolation layer and the back-side insulator. At least one of a portion of the front contact plug and a portion of the back contact plug may be in the etch stop layer.

公开(公告)号：US20220367520A1

公开(公告)日：2022-11-17

申请号：US17380999

申请日：2021-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  SEUNGHYUN SONG ,  KI-IL KIM ,  GUNHO JO ,  KANG-ILL SEO

IPC: H01L27/12 ,  H01L27/088 ,  H01L21/84 ,  H01L21/822 ,  H01L21/8234

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

公开(公告)号：US20240194536A1

公开(公告)日：2024-06-13

申请号：US18215459

申请日：2023-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heesub KIM ,  GUNHO JO ,  BOMI KIM ,  Eunho CHO

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L27/088

Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor structure and a dummy structure on a substrate; forming a first insulating layer between the semiconductor structure and the dummy structure; forming a first space by removing the dummy structure; forming an isolation pattern in the first space; forming a main gate sacrificial pattern crossing the first direction to overlap the semiconductor structure; forming second spaces by removing portions of the semiconductor structure at both sides of the main gate sacrificial pattern, and forming source/drain patterns in the second spaces; forming a second insulating layer on the source/drain patterns; forming a third space by removing the main gate sacrificial pattern, and forming a gate electrode in the third space; and forming fourth spaces by removing the second insulating layer, and forming, in the fourth spaces, contact structures connected to the source/drain patterns and disposed on both sides of the isolation pattern.