公开(公告)号：US20170148914A1

公开(公告)日：2017-05-25

申请号：US15348586

申请日：2016-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongseok LEE ,  Jeongyun LEE ,  Gigwan PARK ,  Keo Myoung SHIN ,  Hyunji KIM ,  Sangduk PARK

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7843 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A semiconductor device includes an active pattern having sidewalls defined by a device isolation pattern disposed on a substrate and an upper portion protruding from a top surface of the device isolation pattern, a liner insulating layer on the sidewalls of the active pattern, a gate structure on the active pattern, and source/drain regions at both sides of the gate structure. The liner insulating layer includes a first liner insulating layer and a second liner insulating layer having a top surface higher than a top surface of the first liner insulating layer. Each of the source/drain regions includes a first portion defined by the second liner insulating layer, and a second portion protruding upward from the second liner insulating layer and covering the top surface of the first liner insulating layer.

公开(公告)号：US20180366583A1

公开(公告)日：2018-12-20

申请号：US16111854

申请日：2018-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Gigwan PARK ,  Junggun YOU ,  DongSuk SHIN ,  Jin-Wook KIM

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L23/535 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/165 ,  H01L27/092 ,  H01L27/11 ,  H01L29/161 ,  H01L29/16

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636

Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.

公开(公告)号：US20170117411A1

公开(公告)日：2017-04-27

申请号：US15288080

申请日：2016-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Gigwan PARK ,  Junggun YOU ,  DongSuk SHIN ,  Jin-Wook KIM

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L23/535 ,  H01L29/06 ,  H01L27/11 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636

Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.