公开(公告)号：US20250014619A1

公开(公告)日：2025-01-09

申请号：US18670910

申请日：2024-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuseong Kang ,  EUNJI LEE

IPC: G11C11/16

Abstract: A memory device includes a memory cell having an access transistor and a variable resistance element, a word line connected to a gate of the access transistor, and a gate driver circuit configured to provide a word line voltage to the word line in a read operation or a write operation, receive, during the read operation, a first power supply voltage from a power terminal and provide a second power supply voltage lower than the first power supply voltage to the word line by attenuating the first power supply voltage to the second power supply voltage, and receive, during the write operation, a third power supply voltage higher than the first power supply voltage from the power terminal and provide the third power supply voltage to the word line without attenuating the third power supply voltage.

公开(公告)号：US12068015B2

公开(公告)日：2024-08-20

申请号：US17894554

申请日：2022-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong Kang ,  Hyuntaek Jung

IPC: G11C8/10 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G11C8/10 ,  G11C11/1655 ,  G11C11/1657

Abstract: A memory device including a memory cell array including a first sub memory cell array including a first memory cell and a second sub memory cell array including a second memory cell, a merged write driver including a first write circuit receiving n-bit data (n being a natural number ≥2) through a write input/output line, outputting a first write voltage to a merged node in response to a first data bit of the n-bit data, and outputting a second write voltage to the merged node in response to a second data bit of the n-bit data, and a column decoder including a first column multiplexer applying a first voltage of the merged node corresponding to the first data bit to the first memory cell and a second column multiplexer applying a second voltage of the merged node corresponding to the second data bit to the second memory cell.

公开(公告)号：US20220343961A1

公开(公告)日：2022-10-27

申请号：US17695941

申请日：2022-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuseong Kang ,  Suk-Soo Pyo

IPC: G11C11/16

Abstract: A memory device which includes a control logic circuit that generates a write enable signal based on a write command, a first memory cell connected with a first word line and a first column line, a first write circuit that receives first write data to be stored in the first memory cell through a first write input/output line and applies a write voltage to a first data line based on the first write data in response to the write enable signal, and a first column multiplexer circuit that selects the first column line and connects the first column line with the first data line in response to a first column select signal, such that the write voltage is applied to the first memory cell. The first write circuit applies the write voltage to a bulk port of the first column multiplexer circuit in response to the write enable signal.

公开(公告)号：US12051456B2

公开(公告)日：2024-07-30

申请号：US17695941

申请日：2022-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuseong Kang ,  Suk-Soo Pyo

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1697 ,  G11C11/161

Abstract: A memory device which includes a control logic circuit that generates a write enable signal based on a write command, a first memory cell connected with a first word line and a first column line, a first write circuit that receives first write data to be stored in the first memory cell through a first write input/output line and applies a write voltage to a first data line based on the first write data in response to the write enable signal, and a first column multiplexer circuit that selects the first column line and connects the first column line with the first data line in response to a first column select signal, such that the write voltage is applied to the first memory cell. The first write circuit applies the write voltage to a bulk port of the first column multiplexer circuit in response to the write enable signal.

公开(公告)号：US12040005B2

公开(公告)日：2024-07-16

申请号：US17870545

申请日：2022-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong Kang

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1655 ,  G11C11/1657

Abstract: A semiconductor device includes a first memory cell array including a plurality of first memory cells, a plurality of first reference cells and a plurality of first dummy cells, a second memory cell array including a plurality of second memory cells, a plurality of second reference cells and a plurality of second dummy cells, an input/output circuit provided between the first memory cell array and the second memory cell array, a first column decoder connected between the first memory cell array and the input/output circuit and a second column decoder connected between the second memory cell array and the input/output circuit. The second column decoder connects one of the plurality of second dummy cells and the plurality of second memory cells to a selected sense amplifier of the input/output circuit, when the first column decoder connects a selected first memory cell to the selected sense amplifier.

公开(公告)号：US11908503B2

公开(公告)日：2024-02-20

申请号：US17711297

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuseong Kang ,  Antonyan Artur ,  Hyuntaek Jung

IPC: G11C11/16 ,  G11C7/14 ,  G11C7/10

CPC classification number: G11C11/1673 ,  G11C7/1039 ,  G11C7/14 ,  G11C11/1655 ,  G11C11/1675 ,  G11C11/1697

Abstract: A nonvolatile memory device includes an array of magnetic memory cells, and control logic circuit having a voltage generator therein, which is configured to generate a gate voltage. A row decoder is provided, which is connected by word lines to the array of magnetic memory cells, and has a word line driver driven therein, which is responsive to the gate voltage. A column decoder is provided, which is connected by bit lines and source lines to the array of magnetic memory cells. A write driver is provided, which has a write voltage generating circuit therein that is configured to output a write voltage, in response to: (i) a reference voltage generated using a replica magnetic memory cell, and (ii) a feedback voltage generated using a magnetic memory cell in which a write operation is to be performed.

公开(公告)号：US20230020262A1

公开(公告)日：2023-01-19

申请号：US17711297

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuseong Kang ,  Antonyan Artur ,  Hyuntaek Jung

IPC: G11C11/16 ,  G11C7/10 ,  G11C7/14

Abstract: A nonvolatile memory device includes an array of magnetic memory cells, and control logic circuit having a voltage generator therein, which is configured to generate a gate voltage. A row decoder is provided, which is connected by word lines to the array of magnetic memory cells, and has a word line driver driven therein, which is responsive to the gate voltage. A column decoder is provided, which is connected by bit lines and source lines to the array of magnetic memory cells. A write driver is provided, which has a write voltage generating circuit therein that is configured to output a write voltage, in response to: (i) a reference voltage generated using a replica magnetic memory cell, and (ii) a feedback voltage generated using a magnetic memory cell in which a write operation is to be performed.