公开(公告)号：US12249976B2

公开(公告)日：2025-03-11

申请号：US18050489

申请日：2022-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Kyu Jang ,  Suk-Soo Pyo

IPC: G11C16/30 ,  H03K17/0812

Abstract: A power switch circuit and non-volatile memory device including the same are provided. The power switch circuit includes a multi-voltage providing circuit configured to receive a first voltage and a second voltage greater than the first voltage, output a third voltage corresponding to the first voltage to a first output terminal, and output a fourth voltage corresponding to the second voltage to a second output terminal. The power switch circuit also includes a leakage current prevention circuit configured to cut off a leakage current flowing through the multi-voltage providing circuit. The multi-voltage providing circuit includes a first inverter which is driven using the second voltage. The leakage current prevention circuit is configured to cut off the leakage current flowing through the first inverter in response to both the first voltage and the second voltage being provided to the multi-voltage providing circuit.

公开(公告)号：US10593402B2

公开(公告)日：2020-03-17

申请号：US16243796

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk-Soo Pyo ,  Hyuntaek Jung ,  Taejoong Song ,  Boyoung Seo

IPC: G11C11/16 ,  G11C13/00

Abstract: A nonvolatile memory device includes a first variable resistance element connected to a first bit line, and a first transmission ;ate connected between the first variable resistance element and a first source line. The first transmission gate includes a first insulating layer formed on a well connected to aground voltage, a first n-channel metal oxide semiconductor (NMOS) transistor formed on the first insulating layer and connected to a first word line, a second insulating layer formed on the well, the second insulating layer being in the same layer as the first insulating layer, and a first p-channel metal oxide semiconductor (PMOS) transistor formed on the second insulating layer and connected to a first write word line.

公开(公告)号：US20190311755A1

公开(公告)日：2019-10-10

申请号：US16450035

申请日：2019-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suk-Soo Pyo ,  Hyun-Taek Jung ,  Tae-Joong Song

IPC: G11C11/16 ,  G11C8/08 ,  G11C13/00

Abstract: A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.

公开(公告)号：US10192618B2

公开(公告)日：2019-01-29

申请号：US15663416

申请日：2017-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk-Soo Pyo ,  Hyuntaek Jung ,  Taejoong Song ,  Boyoung Seo

IPC: G11C13/00

Abstract: An operating method of a nonvolatile memory device includes storing different data in first and second reference cells connected to a word line, checking whether the different data are abnormally stored in the first and second reference cells, and when it is determined that the different data are abnormally stored in the first and second reference cells, swapping the first and second reference cells.

公开(公告)号：US20220343961A1

公开(公告)日：2022-10-27

申请号：US17695941

申请日：2022-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuseong Kang ,  Suk-Soo Pyo

IPC: G11C11/16

Abstract: A memory device which includes a control logic circuit that generates a write enable signal based on a write command, a first memory cell connected with a first word line and a first column line, a first write circuit that receives first write data to be stored in the first memory cell through a first write input/output line and applies a write voltage to a first data line based on the first write data in response to the write enable signal, and a first column multiplexer circuit that selects the first column line and connects the first column line with the first data line in response to a first column select signal, such that the write voltage is applied to the first memory cell. The first write circuit applies the write voltage to a bulk port of the first column multiplexer circuit in response to the write enable signal.

公开(公告)号：US10373664B2

公开(公告)日：2019-08-06

申请号：US15919876

申请日：2018-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suk-Soo Pyo ,  Hyun-Taek Jung ,  Tae-Joong Song

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/56 ,  G11C13/00

Abstract: A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.

公开(公告)号：US10224086B2

公开(公告)日：2019-03-05

申请号：US15816810

申请日：2017-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Shik Kim ,  Suk-Soo Pyo ,  Gwan-Hyeob Koh

IPC: G11C7/04 ,  G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/08

Abstract: A memory device includes at least one reference cell and multiple memory cells. A method of operating the memory device may include detecting a temperature of the memory device and controlling a level of a first read signal applied to the at least one reference cell in accordance with a result of the detecting of the temperature. The method may also include comparing a first sensing value sensed by applying the first read signal to the at least one reference cell with a second sensing value sensed by applying a second read signal to a selected memory cell among the multiple memory cells.

公开(公告)号：US10910030B2

公开(公告)日：2021-02-02

申请号：US16390170

申请日：2019-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Artur Antonyan ,  Hyuntaek Jung ,  Suk-Soo Pyo

IPC: G11C11/16

Abstract: A memory device including a normal memory cell array including a first magneto-resistance memory cell that is connected to a first bit line, a first source line, and a first word line, and configured to receive a selection voltage through the first word line, a monitor memory cell array including a second magneto-resistance memory cell that is connected to a first signal line and a second signal line, a gate of a cell transistor of which is configured to receive a non-selection voltage, and a body bias generator configured to sense a leakage current flowing through the first signal line and control a body voltage provided to each of a body of a cell transistor of the first magneto-resistance memory cell and a body of the cell transistor of the second magneto-resistance memory cell based on the leakage current may be provided.

公开(公告)号：US20200065029A1

公开(公告)日：2020-02-27

申请号：US16394506

申请日：2019-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyun Kim ,  Chankyung Kim ,  Sang-won Shim ,  Suk-Soo Pyo

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

Abstract: An operating method of a storage device which includes a first nonvolatile memory device and a second nonvolatile memory device includes detecting sudden power-off, suspending an operation being performed in the first nonvolatile memory device, in response to the detected sudden power-off, writing suspension information about the suspended operation into the second nonvolatile memory device, and performing a block management operation on the first nonvolatile memory device based on the suspension information written into the second nonvolatile memory device, in power-up after the sudden power-off.

公开(公告)号：US10431300B2

公开(公告)日：2019-10-01

申请号：US15936696

申请日：2018-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suk-Soo Pyo ,  Hyuntaek Jung ,  Taejoong Song

IPC: G11C11/00 ,  G11C13/00 ,  G11C29/50 ,  G11C11/16 ,  G11C5/14 ,  G11C29/02 ,  G11C7/14 ,  G11C8/08 ,  G11C7/22

Abstract: A memory device includes a delay locked loop that generates a first code for delaying a reference clock in a first operation mode that is a normal operation mode, generates a second code for delaying the reference clock in a second operation mode that is a refresh mode, and delays the reference clock in response to one of the first and second codes depending on one of the first and second operation modes, and a data output circuit that outputs a data strobe signal (DQS) using the delayed reference clock.