-
公开(公告)号：US20240363162A1
公开(公告)日：2024-10-31
申请号：US18770397
申请日：2024-07-11
Applicant: Nantero, Inc.
Inventor： Claude L. Bertin
CPC classification number: G11C13/025 , H10K10/50 , H10K19/202 , H10K85/221
Abstract: The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.
-
公开(公告)号：US20240038299A1
公开(公告)日：2024-02-01
申请号：US18377623
申请日：2023-10-06
Applicant: Nantero, Inc.
Inventor： Jia Luo , Lee E. Cleveland , Ton Yan Tony Chan
CPC classification number: G11C11/5664 , G11C13/0014 , G11C13/0069 , G11C13/003 , G11C13/025 , H10K10/50 , H10K19/202 , H10K85/211 , H10K85/221 , H10B63/84 , H10N70/841 , H10N70/8845 , G11C13/004 , G11C2213/35 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C2213/79
Abstract: The present disclosure generally relates to combinations of resistive change elements and resistive change element arrays thereof. The present disclosure also generally relates to combinational resistive change elements and combinational resistive change element arrays thereof. The present disclosure additionally generally relates to devices and methods for programming and accessing combinations of resistive change elements. The present disclosure further generally relates to devices and methods for programming and accessing combinational resistive change elements.
-
公开(公告)号：US12127416B2
公开(公告)日：2024-10-22
申请号：US17639579
申请日：2020-07-16
Applicant: HIROSHIMA UNIVERSITY
Inventor： Sadafumi Nishihara , Masaru Fujibayashi , Katsuya Inoue , Masahiro Sadakane
CPC classification number: H10K10/701 , C01B25/45 , H10B53/30 , H10K10/50 , H10K19/202
Abstract: A molecular memory recording molecular polarization of a single-molecule electret, and the single-molecule electret includes a cluster skeleton 100 having a continuous hole 101 and a plurality of stable ionic sites 102a, 102b and a metal ion M. The molecular polarization is shown in a state in which the metal ion is included in the stable ionic site. The molecular polarization is changed by movement of the metal ion to the other hollow stable ionic site by application of an electric field. The recordkeeping time of the molecular memory in a temperature range of −100° C. to 100° C. based on the ion radius of the metal ion is 3.0×10−2 seconds to 9.1×1022 seconds. Based on the recordkeeping time, the molecular memory is used as any of a volatile memory, a non-volatile memory, and a storage class memory.
-
公开(公告)号：US12068029B2
公开(公告)日：2024-08-20
申请号：US18370541
申请日：2023-09-20
Applicant: Nantero, Inc.
Inventor： Claude L. Bertin
CPC classification number: G11C13/025 , H10K10/50 , H10K19/202 , H10K85/221
Abstract: The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.
-
公开(公告)号：US11964994B2
公开(公告)日：2024-04-23
申请号：US17109668
申请日：2020-12-02
Applicant: Alliance for Sustainable Energy, LLC , University of Utah Research Foundation , Duke University
Inventor： Matthew C. Beard , Haipeng Lu , Annalise Elizabeth Maughan , Joseph Jonathan Berry , Zeev Valentine Vardeny , Chuanxiao Xiao , Volker Wolfgang Blum , David Brian Mitzi
IPC: C07F7/24 , C07C211/65 , C07F7/22 , H10K10/50 , H10K85/50
CPC classification number: C07F7/24 , C07C211/65 , C07F7/2208 , H10K85/50 , H10K10/50
Abstract: The present disclosure relates to a composition that includes a perovskite of A2BX4, where A includes an R-form of a chiral molecule of at least one of
and/or an S-form of the chiral molecule, B includes a cation, X includes an anion, R1 includes a first carbon chain having between 2 and 5 carbon atoms, R2 includes at least one of a hydrogen atom, a halogen atom, a carboxylic acid group, an alkoxy group, and/or a second carbon chain, and R3 includes a third carbon chain.-
Patent Agency Ranking
公开(公告)号：US11984514B2
公开(公告)日：2024-05-14
申请号：US18324638
申请日：2023-05-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinseong Heo , Taehwan Moon , Hagyoul Bae , Seunggeol Nam , Sangwook Kim , Kwanghee Lee
CPC classification number: H01L29/86 , H10B69/00 , H10K10/50 , H10K19/00 , H10K19/201
Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.
-
公开(公告)号：US11842771B2
公开(公告)日：2023-12-12
申请号：US17509941
申请日：2021-10-25
Applicant: International Business Machines Corporation
Inventor： Ali Afzali-Ardakani , James B. Hannon
CPC classification number: G11C13/0069 , G11C13/004 , G11C13/0016 , H10K10/50 , H10K19/202 , H10K71/211 , H10K85/111 , H10K85/60
Abstract: Programmable memory devices having a cross-point array of polymer junctions with individually-programmed conductances are provided. In one aspect, a method of forming a memory device includes: forming first metal lines on an insulating substrate; forming polymeric resistance elements on the first metal lines; and forming second metal lines over the polymeric resistance elements with a single one of the polymeric resistance elements present at each intersection of the first/second metal lines forming a cross-point array. A memory device and a method of operating a memory device are also provided.
-
公开(公告)号：US20230309327A1
公开(公告)日：2023-09-28
申请号：US18188360
申请日：2023-03-22
Inventor： Sang Su PARK , Sung Yool Choi , Jun Hwe Cha , Jung Yeop Oh
CPC classification number: H10K10/50 , H10K85/111 , H10K10/82 , H10B63/20 , H10K71/10
Abstract: A memristor device, a fabricating method thereof, a synaptic device including the memristor device, and a neuromorphic device including the synaptic device are provided. The memristor device includes a first electrode, a second electrode spaced apart from the first electrode, a resistance change layer disposed between the first electrode and the second electrode and including a polymer, and an insertion layer disposed between the first electrode and the resistance change layer and including an oxide. An electrochemical metallization mechanism (ECM) filament is formed in the resistance change layer, and a valence change mechanism (VCM) filament is formed in the insertion layer. The memristor device has a synaptic characteristic according to a change in resistance of the resistance change layer. The insertion layer includes an Al2O3 layer. The insertion layer includes an Al2O3 layer formed by an atomic layer deposition (ALD) process using a temperature of about 200° C. or higher.
-
公开(公告)号：US12016188B2
公开(公告)日：2024-06-18
申请号：US17840213
申请日：2022-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyuncheol Kim , Yongseok Kim , Dongsoo Woo , Kyunghwan Lee
CPC classification number: H10K19/202 , G11C13/0014 , G11C13/0069 , H10K10/50 , H10K85/221
Abstract: A semiconductor memory device includes a plurality of semiconductor patterns extending in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas; and a plurality of resistive switch units respectively connected to first sidewalls of the semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first and second electrodes and including carbon nanotubes.
-
公开(公告)号：US11943940B2
公开(公告)日：2024-03-26
申请号：US17253088
申请日：2019-07-11
Applicant: The Regents of the University of California , University of Washington , Emory University
Inventor： Joshua Hihath , Manjeri P. Anantram , Yonggang Ke
CPC classification number: H10K19/202 , H10K10/50 , H10K85/761
Abstract: A nanostructured cross-wire memory architecture is provided that can interface with conventional semiconductor technologies and be electrically accessed and read. The architecture links lower and upper sets of generally parallel nanowires oriented crosswise, with a memory element that has a characteristic conductance. Each nanowire end is attached to an electrode. Conductance of the linkages in the gap between the wires encodes the information. The nanowires may be highly-conductive, self-assembled, nucleic acid-based nanowires enhanced with dopants including metal ions, carbon, metal nanoparticles and intercalators. Conductance of the memory elements can be controlled by sequence, length, conformation, doping, and number of pathways between nanowires. A diode can also be connected in series with each of the memory elements. Linkers may also be redox or electroactive switching molecules or nanoparticles where the charge state changes the resistance of the memory element.
-
-
-
-
-
-
-
-
-
Search Results
20
records
(took 0.017 seconds)
