公开(公告)号：US10763834B2

公开(公告)日：2020-09-01

申请号：US16407757

申请日：2019-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho Young Shin

IPC: H01L27/11 ,  H03K3/037 ,  H03K19/0185 ,  G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  G11C16/14 ,  G11C16/10

Abstract: A latch circuit including: a first inverter having a first pull-up transistor connected between a first power supply node and a first output node, and a first pull-down transistor connected between a second power supply node and the first output node; a second inverter having a second pull-up transistor connected between the first power supply node and a second output node, and a second pull-down transistor connected between the second power supply node and the second output node; a first current control transistor connected between the first pull-up transistor and the first output node; a second current control transistor connected between the second pull-up transistor and the second output node; a third current control transistor connected between the first pull-down transistor and the first output node; and a fourth current control transistor connected between the second pull-down transistor and the second output node.

公开(公告)号：US10707749B2

公开(公告)日：2020-07-07

申请号：US16414972

申请日：2019-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho Young Shin

IPC: H02M3/07 ,  G11C16/30 ,  G11C16/14 ,  G11C16/08

Abstract: A charge pump includes a first pumping capacitor configured to pump a first voltage of a first node, in response to a first clock signal, a gate pumping capacitor configured to pump a second voltage of a second node, in response to a second clock signal, a charge transfer transistor including a first source connected to a first one of a third node and the first node, a first gate connected to the second node, and a first drain connected to a remaining one of the first node and the third node, a gate control transistor including a second source connected to the first one of the third node and the first node, a second gate connected to the remaining one of the first node and the third node, and a second drain connected to the second node, and a gate discharge or charge unit.

公开(公告)号：US11062776B2

公开(公告)日：2021-07-13

申请号：US16731288

申请日：2019-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jin Shin ,  Ji-Sung Kim ,  Ho Young Shin ,  Myeong Hee Oh

IPC: G11C5/14 ,  G11C16/12 ,  G11C16/30

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells that are programmed based on a high voltage, a high voltage generator to generate the high voltage by boosting an input voltage based on a pumping clock, a pumping clock generator to generate the pumping clock, a high voltage detector to generate a detection signal by comparing an adjustment voltage with a reference voltage, a programming current controller to adjust a programming current flowing through each of selected memory cells of the plurality of memory cells; and a control logic to adjust a frequency of the pumping clock and a current driving capability of the programming current based on the detection signal during a programming period with respect to the selected memory cells. The detection signal includes information indicating whether the high voltage reaches to a target voltage.

公开(公告)号：US09928917B2

公开(公告)日：2018-03-27

申请号：US15440625

申请日：2017-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Jin Shin ,  Ho Young Shin

IPC: G11C7/00 ,  G11C16/24 ,  G11C16/04 ,  G11C16/30 ,  G11C11/4074 ,  G11C11/417

CPC classification number: G11C16/24 ,  G11C7/04 ,  G11C7/067 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/417 ,  G11C11/419 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2207/063

Abstract: A memory device includes a memory cell, a bit line connected to the memory cell, a control voltage generator configured to generate a proportional to absolute temperature (PTAT) current and generate an analog control voltage inversely proportional to the PTAT current, and a load current control circuit configured to control a first load current supplied to the bit line based on the analog control voltage.