公开(公告)号：US20180358056A1

公开(公告)日：2018-12-13

申请号：US15854551

申请日：2017-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho LEE ,  Gwanhyeob KOH ,  Junhee LIM ,  Hongsoo KIM ,  Chang-hoon JEON

IPC: G11C5/06 ,  G11C16/04 ,  G11C11/16 ,  H01L25/18 ,  H01L27/1157 ,  H01L27/22 ,  H01L27/11573 ,  H01L43/10

CPC classification number: G11C5/06 ,  G11C11/005 ,  G11C11/161 ,  G11C13/0002 ,  G11C13/0004 ,  G11C16/0483 ,  G11C2213/72 ,  G11C2213/76 ,  H01L25/18 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/222 ,  H01L43/10

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.

公开(公告)号：US20190267046A1

公开(公告)日：2019-08-29

申请号：US16411106

申请日：2019-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho LEE ,  Gwanhyeob KOH ,  Junhee LIM ,  Hongsoo KIM ,  Chang-hoon JEON

IPC: G11C5/06 ,  H01L27/11573 ,  H01L27/22 ,  H01L27/1157 ,  H01L43/10 ,  G11C13/00 ,  H01L25/18 ,  G11C11/16 ,  G11C16/04

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.

公开(公告)号：US20250105215A1

公开(公告)日：2025-03-27

申请号：US18624892

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keumhyo KANG ,  Hongsoo KIM ,  Jeon Il LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H10B12/00

Abstract: Disclosed are semiconductor packages and electronic systems. The semiconductor package comprises a first semiconductor chip that includes a first peripheral circuit structure and a first memory cell structure on the first peripheral circuit structure and a second semiconductor chip that includes a second peripheral circuit structure and a second memory cell structure on the second peripheral circuit structure. The first peripheral circuit structure includes a first substrate, a controller on the first substrate, and a first driver circuit on the first substrate. The second peripheral circuit structure includes a second substrate and a second driver circuit on the second substrate. The controller is electrically connected to the first driver circuit and the second driver circuit.