公开(公告)号：US11876083B2

公开(公告)日：2024-01-16

申请号：US17407647

申请日：2021-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Kim ,  Ji Hwang Kim ,  Hwan Pil Park ,  Jongbo Shim

IPC: H01L23/02 ,  H01L25/10 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L25/105 ,  H01L21/4882 ,  H01L25/0655 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.

公开(公告)号：US12283578B2

公开(公告)日：2025-04-22

申请号：US17710830

申请日：2022-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong Hyun Lee ,  Hwan Pil Park ,  Jong Bo Shim

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor package includes; a substrate including a first insulating layer and a first conductive pattern in the first insulating layer, a first semiconductor chip on the substrate, an interposer spaced apart from the first semiconductor chip in a direction perpendicular to an upper surface of the substrate and including a second insulating layer and a second conductive pattern in the second insulating layer, a first element between the first semiconductor chip and the interposer, a connection member between the substrate and the interposer, and a mold layer covering side surfaces of the first semiconductor chip and side surfaces of the first element.

公开(公告)号：US11239175B2

公开(公告)日：2022-02-01

申请号：US16865470

申请日：2020-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Ho Kim ,  Hwan Pil Park ,  Sung-Chul Kim ,  Key-One Ahn

IPC: H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/38 ,  H01L23/31

Abstract: A semiconductor package includes: a substrate; a semiconductor chip disposed on a first surface of the substrate; solder bumps disposed between a first surface of the semiconductor chip and the substrate; and a redistribution layer provided on a second surface, opposite to the first surface, of the semiconductor chip. The substrate includes substrate patterns, and the substrate patterns cover a second surface of the substrate. The substrate patterns cover 60% to 100% of a total area of the second surface of the substrate.

公开(公告)号：US11948873B2

公开(公告)日：2024-04-02

申请号：US17555583

申请日：2021-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyun Lee ,  Dongwook Kim ,  Hwan Pil Park ,  Jongbo Shim

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L23/16 ,  H01L23/31 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/13001 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/1301 ,  H01L2224/13016 ,  H01L2224/1302 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/13563 ,  H01L2225/1058

Abstract: A semiconductor package including: a first substrate; a first semiconductor device on the first substrate; a first mold layer covering the first semiconductor device; a second substrate on the first mold layer; a support solder ball interposed between the first substrate and the second substrate, and electrically disconnected from the first substrate or the second substrate, wherein the support solder ball includes a core and is disposed near a first sidewall of the first semiconductor device; and a substrate connection solder ball disposed between the first sidewall of the first semiconductor device and the support solder ball to electrically connect the first substrate to the second substrate, wherein a top surface of the first semiconductor device has a first height from a top surface of the first substrate, and the core has a second height which is equal to or greater than the first height.

公开(公告)号：US11908806B2

公开(公告)日：2024-02-20

申请号：US17501008

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Ho Kim ,  Ji Hwang Kim ,  Hwan Pil Park ,  Jong Bo Shim

IPC: H01L23/552 ,  H01L23/498 ,  H01L21/56 ,  H01L23/42 ,  H01L21/48

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838

Abstract: A semiconductor package includes a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern; a first semiconductor chip placed on an upper surface of the first substrate; a ball array structure that is placed on the upper surface of the first substrate along a perimeter of the first semiconductor chip and is electrically connected to the ground pattern; and a shielding structure placed on the upper surface of the first semiconductor chip and in contact with the upper surface of the ball array structure. The ball array structure has a closed loop shape, and includes a solder ball portion and a connecting portion that connects adjacent solder ball portions. A maximum width of the solder ball portion is greater than a width of the connecting portion in a direction perpendicular to an extension direction of the connecting portion.

公开(公告)号：US11854989B2

公开(公告)日：2023-12-26

申请号：US17167789

申请日：2021-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongho Kim ,  Jongbo Shim ,  Hwan Pil Park ,  Choongbin Yim ,  Jungwoo Kim

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/0651 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/19103

Abstract: A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other.