公开(公告)号：US20190066748A1

公开(公告)日：2019-02-28

申请号：US15946055

申请日：2018-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Min Lee ,  Hyemin Shin ,  Jung Hyuk Lee ,  Hyunsung Jung

IPC: G11C11/16 ,  H01L23/528 ,  H01L27/22 ,  H01L43/08 ,  G11C29/42 ,  H01F10/32

Abstract: A memory device may include a selected bit line connected to a first node and configured to receive a first current, a selected memory cell connected to the selected bit line, a reference bit line connected to a second node and configured to receive a second current, a reference memory cell connected between the reference bit line and a reference source line, a sub bit line connected to the second node, a sub memory cell connected between the sub bit line and a sub source line, and a sense amplifier configured to sense a voltage difference between the first node and the second node to determine data read from a selected memory cell connected to the selected bit line. The sub memory cell may include a cell transistor. A gate electrode of the cell transistor may be connected to the sub source line.

公开(公告)号：US10672447B2

公开(公告)日：2020-06-02

申请号：US16262366

申请日：2019-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsung Jung ,  Hyemin Shin ,  Yoonjong Song ,  Jung Hyuk Lee

IPC: G11C16/10 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: Disclosed is a memory device. The memory device includes a memory cell array that includes a target cell, a row decoder that drive a word line, and a write driver and sense amplifier that are configured to drive a bit line and a source line. The row decoder is configured to drive the word line in a first program operation and a second program operation. Between a start of the first program operation and an end of the second program operation, the write driver and sense amplifier are configured to continuously drive a bit line connected to the target cell with a second driving voltage or drive a source line connected to the target cell with a third driving voltage.

公开(公告)号：US10255959B2

公开(公告)日：2019-04-09

申请号：US15946055

申请日：2018-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Min Lee ,  Hyemin Shin ,  Jung Hyuk Lee ,  Hyunsung Jung

IPC: G11C11/00 ,  G11C11/16 ,  H01L23/528 ,  H01L27/22 ,  H01L43/08 ,  G11C29/42 ,  H01F10/32

Abstract: A memory device may include a selected bit line connected to a first node and configured to receive a first current, a selected memory cell connected to the selected bit line, a reference bit line connected to a second node and configured to receive a second current, a reference memory cell connected between the reference bit line and a reference source line, a sub bit line connected to the second node, a sub memory cell connected between the sub bit line and a sub source line, and a sense amplifier configured to sense a voltage difference between the first node and the second node to determine data read from a selected memory cell connected to the selected bit line. The sub memory cell may include a cell transistor. A gate electrode of the cell transistor may be connected to the sub source line.