CLOCK GENERATING CIRCUIT AND WIRELESS COMMUNICATION DEVICE INCLUDING THE SAME

    公开(公告)号:US20220368513A1

    公开(公告)日:2022-11-17

    申请号:US17586182

    申请日:2022-01-27

    Abstract: A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.

    MEMORY DEVICE CONFIGURED TO PERFORM ASYMMETRIC WRITE OPERATION ACCORDING TO WRITE DIRECTION

    公开(公告)号:US20200090722A1

    公开(公告)日:2020-03-19

    申请号:US16507536

    申请日:2019-07-10

    Abstract: Disclosed are memory devices including a variable resistance memory cell and a word line control circuit. A memory device including a variable resistance memory cell including a variable resistance element, a first cell transistor, and a second cell transistor, a first end of the variable resistance element connected to a bit line, a second end of the variable resistance element, a first end of the first cell transistor, and a first end of the second cell transistor connected to the common node, a second end of the first cell transistor and a second end of the second cell transistor connected to a source line, and a word line control circuit configured to separate a sub word line connected to a gate electrode of the second cell transistor from a word line connected to a gate electrode of the first cell transistor in a first write operation and to connect the word line and the sub word line to each other in a second write operation may be provided.

    MEMORY DEVICES CONFIGURED TO PREVENT READ FAILURE DUE TO LEAKAGE CURRENT INTO BIT LINE

    公开(公告)号:US20190066748A1

    公开(公告)日:2019-02-28

    申请号:US15946055

    申请日:2018-04-05

    Abstract: A memory device may include a selected bit line connected to a first node and configured to receive a first current, a selected memory cell connected to the selected bit line, a reference bit line connected to a second node and configured to receive a second current, a reference memory cell connected between the reference bit line and a reference source line, a sub bit line connected to the second node, a sub memory cell connected between the sub bit line and a sub source line, and a sense amplifier configured to sense a voltage difference between the first node and the second node to determine data read from a selected memory cell connected to the selected bit line. The sub memory cell may include a cell transistor. A gate electrode of the cell transistor may be connected to the sub source line.

    Clock generating circuit and wireless communication device including the same

    公开(公告)号:US11728961B2

    公开(公告)日:2023-08-15

    申请号:US17586182

    申请日:2022-01-27

    CPC classification number: H04L7/0037 H04L7/033

    Abstract: A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.

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