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    DRUM WASHING MACHINE
    1.
    发明申请
    DRUM WASHING MACHINE 有权
    滚筒洗衣机

    公开(公告)号：US20140047869A1

    公开(公告)日：2014-02-20

    申请号：US13966858

    申请日：2013-08-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jin Doo Kim ,  Jung Hyuk Lee ,  Kyung Up Lim ,  Nam Kyu Jun ,  Yong Sok Lee ,  Hyung Sub Lim ,  Min Hee Kang

    IPC: D06F39/08

    CPC classification number: D06F39/083 ,  D06F25/00 ,  D06F58/22

    Abstract: A drum washing machine and a control method thereof. The drum washing machine includes a cabinet, a tub including a first tub part and a second tub part, a drum, an inlet provided at one side of the second tub part and supplying condensed water, and at least one flow path provided on one surface from among the inner surfaces of the second tub part opposite the drum and guiding flow of the condensed water to increase a contact area between the condensed water supplied from the inlet and the second tub part. The drum washing machine improves the structure of the tub to effectively inject condensed water, and may thus increase condensing efficiency. Further, the drum washing machine improves the structures of the tub and the drying duct, and may thus prevent accumulation of lint and lowering of performance of the drum washing machine.

    Abstract translation: 滚筒洗衣机及其控制方法。 滚筒洗衣机包括机壳，包括第一桶部分和第二桶部分的桶，滚筒，设置在第二桶部分的一侧并供应冷凝水的入口，以及设置在一个表面上的至少一个流路 从所述第二桶部分的与所述滚筒相对的内表面和所述冷凝水的引导流量增加从所述入口和所述第二桶部分供应的冷凝水之间的接触面积。 滚筒洗衣机改善了桶的结构以有效地注入冷凝水，从而可以提高冷凝效率。 此外，滚筒洗衣机改善了桶和干燥管的结构，并且因此可以防止棉绒的积聚和降低滚筒洗衣机的性能。

    Test method for memory device, operating method of test device testing memory device, and memory device with self-test function
    2.
    发明授权
    Test method for memory device, operating method of test device testing memory device, and memory device with self-test function 有权

    公开(公告)号：US11367501B2

    公开(公告)日：2022-06-21

    申请号：US17035917

    申请日：2020-09-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung Hyuk Lee

    IPC: G11C29/42 ,  G11C11/16 ,  G11C29/44 ,  G06F11/10

    Abstract: A test method for a memory device including a plurality of memory cells includes generating a first test pattern, performing a first pattern write operation of writing the first test pattern in the plurality of memory cells, reading first data from the plurality of memory cells in which the first test pattern was written, generating a second test pattern based on the first data, and performing a second pattern write operation of writing the second test pattern in the plurality of memory cells. The second test pattern is generated such that a write operation is skipped with regard to failure cells from among the plurality of memory cells at which a write failure occurs, during the second pattern write operation.

    Semiconductor devices
    3.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US10818727B2

    公开(公告)日：2020-10-27

    申请号：US16161370

    申请日：2018-10-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myoungsu Son ,  Seung Pil Ko ,  Jung Hyuk Lee ,  Shinhee Han ,  Gwan-Hyeob Koh ,  Yoonjong Song

    IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  H01L23/522

    Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

    Drum washing machine
    4.
    发明授权
    Drum washing machine 有权

    公开(公告)号：US09695541B2

    公开(公告)日：2017-07-04

    申请号：US13966858

    申请日：2013-08-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jin Doo Kim ,  Jung Hyuk Lee ,  Kyung Up Lim ,  Nam Kyu Jun ,  Yong Sok Lee ,  Hyung Sub Lim ,  Min Hee Kang

    IPC: D06F39/08 ,  D06F58/22 ,  D06F25/00

    CPC classification number: D06F39/083 ,  D06F25/00 ,  D06F58/22

    Abstract: A drum washing machine and a control method thereof. The drum washing machine includes a cabinet, a tub including a first tub part and a second tub part, a drum, an inlet provided at one side of the second tub part and supplying condensed water, and at least one flow path provided on one surface from among the inner surfaces of the second tub part opposite the drum and guiding flow of the condensed water to increase a contact area between the condensed water supplied from the inlet and the second tub part. The drum washing machine improves the structure of the tub to effectively inject condensed water, and may thus increase condensing efficiency. Further, the drum washing machine improves the structures of the tub and the drying duct, and may thus prevent accumulation of lint and lowering of performance of the drum washing machine.

    Test method for memory device, operation method of test device testing memory device, and memory device with self-test function
    6.
    发明授权
    Test method for memory device, operation method of test device testing memory device, and memory device with self-test function 有权

    公开(公告)号：US11600353B2

    公开(公告)日：2023-03-07

    申请号：US17827845

    申请日：2022-05-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung Hyuk Lee

    IPC: G11C29/42 ,  G11C11/16 ,  G06F11/10 ,  G11C29/44

    Abstract: A test method for a memory device including a plurality of memory cells includes generating a first test pattern, performing a first pattern write operation of writing the first test pattern in the plurality of memory cells, reading first data from the plurality of memory cells in which the first test pattern was written, generating a second test pattern based on the first data, and performing a second pattern write operation of writing the second test pattern in the plurality of memory cells. The second test pattern is generated such that a write operation is skipped with regard to failure cells from among the plurality of memory cells at which a write failure occurs, during the second pattern write operation.

    Memory device and programming method
    7.
    发明授权
    Memory device and programming method 审中-公开

    公开(公告)号：US10672447B2

    公开(公告)日：2020-06-02

    申请号：US16262366

    申请日：2019-01-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsung Jung ,  Hyemin Shin ,  Yoonjong Song ,  Jung Hyuk Lee

    IPC: G11C16/10 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

    Abstract: Disclosed is a memory device. The memory device includes a memory cell array that includes a target cell, a row decoder that drive a word line, and a write driver and sense amplifier that are configured to drive a bit line and a source line. The row decoder is configured to drive the word line in a first program operation and a second program operation. Between a start of the first program operation and an end of the second program operation, the write driver and sense amplifier are configured to continuously drive a bit line connected to the target cell with a second driving voltage or drive a source line connected to the target cell with a third driving voltage.

    Nonvolatile memory device having resistive memory cells and a controller to detect fail cells, and electronic device including the same
    9.
    发明授权
    Nonvolatile memory device having resistive memory cells and a controller to detect fail cells, and electronic device including the same 有权

    公开(公告)号：US11625188B2

    公开(公告)日：2023-04-11

    申请号：US17172299

    申请日：2021-02-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung Hyuk Lee ,  Hye Min Shin ,  Kang Ho Lee

    IPC: G06F3/06 ,  G06F11/10

    Abstract: A memory device includes a first nonvolatile memory including a resistive memory cell; and a controller. The controller may be configured to provide the first nonvolatile memory with a first data, a first program command, and a first address. The controller may be configured to receive a second data, which is a verify read from the resistive memory cell programmed with the first data, from the first nonvolatile memory in response to the first program command. The controller may be configured to compare the first data with the second data to detect a number of fail cells. When the number of detected fail cells is greater than a reference value, the controller may be configured to generate a third data obtained by inversing the first data, and provide the third data to the first nonvolatile memory. The first data may include an inversion flag bit.

    MEMORY DEVICES CONFIGURED TO PREVENT READ FAILURE DUE TO LEAKAGE CURRENT INTO BIT LINE
    10.
    发明申请
    MEMORY DEVICES CONFIGURED TO PREVENT READ FAILURE DUE TO LEAKAGE CURRENT INTO BIT LINE 审中-公开

    公开(公告)号：US20190066748A1

    公开(公告)日：2019-02-28

    申请号：US15946055

    申请日：2018-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung Min Lee ,  Hyemin Shin ,  Jung Hyuk Lee ,  Hyunsung Jung

    IPC: G11C11/16 ,  H01L23/528 ,  H01L27/22 ,  H01L43/08 ,  G11C29/42 ,  H01F10/32

    Abstract: A memory device may include a selected bit line connected to a first node and configured to receive a first current, a selected memory cell connected to the selected bit line, a reference bit line connected to a second node and configured to receive a second current, a reference memory cell connected between the reference bit line and a reference source line, a sub bit line connected to the second node, a sub memory cell connected between the sub bit line and a sub source line, and a sense amplifier configured to sense a voltage difference between the first node and the second node to determine data read from a selected memory cell connected to the selected bit line. The sub memory cell may include a cell transistor. A gate electrode of the cell transistor may be connected to the sub source line.

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