公开(公告)号：US20240422966A1

公开(公告)日：2024-12-19

申请号：US18736748

申请日：2024-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yanghee Lee ,  Jonghyuk Park ,  Hyesung Park ,  Seungji Kang ,  Seongeun Kim ,  Dongwon Lee ,  Juyeon Han

IPC: H10B12/00 ,  H01L23/528

Abstract: An integrated circuit device includes a substrate having a memory cell area and a peripheral circuit area extending around the memory cell area, cell transistors in the memory cell area, and a peripheral circuit transistor in the peripheral circuit area. The device further includes: a capacitor structure including lower electrodes on the cell transistors, a dielectric layer on a surface of the lower electrodes, an upper material layer on the dielectric layer, and a metal plate layer on the upper material layer; an interlayer insulating layer on the metal plate layer in the memory cell area and on the peripheral circuit transistor in the peripheral circuit area; and an etch stop pattern in the interlayer insulating layer at a boundary portion of the memory cell area and the peripheral circuit area. The etch stop pattern is spaced laterally from a sidewall of the metal plate layer and extends vertically.

公开(公告)号：US11222897B2

公开(公告)日：2022-01-11

申请号：US16819920

申请日：2020-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyesung Park ,  Jinwoo Bae ,  Youngho Koh ,  Jonghyuk Park ,  Boun Yoon ,  Myungjae Jang

IPC: H01L27/108

Abstract: A semiconductor device including a substrate having a cell region and a peripheral region; a cell gate structure disposed on the cell region; a first impurity region and a second impurity region, arranged on first and second sides of the cell gate structure in the cell region; a bit line structure disposed on the cell gate structure and connected to the first impurity region; a peripheral gate structure disposed on the peripheral region; a peripheral capping layer disposed on the peripheral region, covering the peripheral gate structure, and having an upper surface at substantially the same level as an upper end of the bit line structure; and a cell contact structure disposed on the second impurity region, and having a conductive barrier and a contact material layer on the conductive barrier, wherein the conductive barrier covers the upper end of the bit line structure.

公开(公告)号：US20180166529A1

公开(公告)日：2018-06-14

申请号：US15831757

申请日：2017-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyesung Park ,  Suyoung Shin ,  Jonghyuk Park ,  Boun Yoon ,  llyoung Yoon ,  Sangyeol Kang ,  SeungHo Park ,  Yanghee Lee ,  Wooin Lee

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/84 ,  H01L27/10808 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/90

Abstract: A semiconductor memory devices and methods of fabricating the same are disclosed. For example, the semiconductor memory device including a semiconductor substrate including a cell area and a peripheral area, a plurality of bottom electrodes on the semiconductor substrate at the cell area, a dielectric layer conformally covering top surfaces and sidewalls of the bottom electrodes, and an upper electrode on the dielectric layer and filling between the bottom electrodes may be provided. A surface roughness of a top surface of the upper electrode may be less than a surface roughness of a side surface of the upper electrode.

公开(公告)号：US10756092B2

公开(公告)日：2020-08-25

申请号：US16814387

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyuk Park ,  Byoungho Kwon ,  Inho Kim ,  Hyesung Park ,  Jin-Woo Bae ,  Yanghee Lee ,  Inseak Hwang

IPC: H01L27/108 ,  H01L21/66

Abstract: A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion.

公开(公告)号：US20180366468A1

公开(公告)日：2018-12-20

申请号：US16110658

申请日：2018-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyuk PARK ,  Byoungho Kwon ,  Inho Kim ,  Hyesung Park ,  Jin-Woo Bae ,  Yanghee Lee ,  Inseak Hwang

IPC: H01L27/108 ,  H01L21/66

CPC classification number: H01L27/10855 ,  H01L22/32 ,  H01L22/34 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10876 ,  H01L27/10894

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a semiconductor substrate including a first region and a second region, a dummy separation pattern provided on the second region of the semiconductor substrate to have a recessed region at its upper portion, a first electrode provided on the first region of the semiconductor substrate, a dielectric layer covering the first electrode, a second electrode provided on the dielectric layer, and a remaining electrode pattern provided in the recessed region. The second electrode and the remaining electrode pattern may be formed of a same material.

公开(公告)号：US11183501B2

公开(公告)日：2021-11-23

申请号：US16819920

申请日：2020-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyesung Park ,  Jinwoo Bae ,  Youngho Koh ,  Jonghyuk Park ,  Boun Yoon ,  Myungjae Jang

IPC: H01L27/108

Abstract: A semiconductor device including a substrate having a cell region and a peripheral region; a cell gate structure disposed on the cell region; a first impurity region and a second impurity region, arranged on first and second sides of the cell gate structure in the cell region; a bit line structure disposed on the cell gate structure and connected to the first impurity region; a peripheral gate structure disposed on the peripheral region; a peripheral capping layer disposed on the peripheral region, covering the peripheral gate structure, and having an upper surface at substantially the same level as an upper end of the bit line structure; and a cell contact structure disposed on the second impurity region, and having a conductive barrier and a contact material layer on the conductive barrier, wherein the conductive barrier covers the upper end of the bit line structure.

公开(公告)号：US10777560B2

公开(公告)日：2020-09-15

申请号：US16833914

申请日：2020-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyuk Park ,  Byoungho Kwon ,  Inho Kim ,  Hyesung Park ,  Jin-Woo Bae ,  Yanghee Lee ,  Inseak Hwang

IPC: H01L27/108 ,  H01L21/66

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a semiconductor substrate including a first region and a second region, a dummy separation pattern provided on the second region of the semiconductor substrate to have a recessed region at its upper portion, a first electrode provided on the first region of the semiconductor substrate, a dielectric layer covering the first electrode, a second electrode provided on the dielectric layer, and a remaining electrode pattern provided in the recessed region. The second electrode and the remaining electrode pattern may be formed of a same material.

公开(公告)号：US10748906B2

公开(公告)日：2020-08-18

申请号：US16110658

申请日：2018-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyuk Park ,  Byoungho Kwon ,  Inho Kim ,  Hyesung Park ,  Jin-Woo Bae ,  Yanghee Lee ,  Inseak Hwang

IPC: H01L27/108 ,  H01L21/66

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a semiconductor substrate including a first region and a second region, a dummy separation pattern provided on the second region of the semiconductor substrate to have a recessed region at its upper portion, a first electrode provided on the first region of the semiconductor substrate, a dielectric layer covering the first electrode, a second electrode provided on the dielectric layer, and a remaining electrode pattern provided in the recessed region. The second electrode and the remaining electrode pattern may be formed of a same material.