利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.016 秒)

    Three-dimensional semiconductor memory device
    2.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US10916554B2

    公开(公告)日：2021-02-09

    申请号：US16793301

    申请日：2020-02-18

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Miso Shin ,  Myeongan Kwon ,  Chungki Min ,  Byoungho Kwon ,  Boun Yoon

    IPC分类号： H01L27/11548 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

    摘要： Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.

    SEMICONDUCTOR MEMORY DEVICES
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190081102A1

    公开(公告)日：2019-03-14

    申请号：US15919639

    申请日：2018-03-13

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kichul Park ,  Ki-Woong Kim ,  Hansol Seok ,  Byoungho Kwon ,  Boun Yoon

    IPC分类号： H01L27/22 ,  H01L23/522 ,  H01L43/08 ,  H01L43/02 ,  H01F10/32 ,  H01L23/532 ,  H01L23/528 ,  G11C11/16 ,  H01L43/12 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3213

    摘要： A semiconductor memory device may include a selection transistor on a semiconductor substrate, an interlayered insulating layer covering the selection transistor, a lower contact plug coupled to a drain region of the selection transistor and configured to penetrate the interlayered insulating layer, and a magnetic tunnel junction pattern coupled to the lower contact plug. The lower contact plug may include a metal pattern and a capping metal pattern in contact with a top surface of the metal pattern. The capping metal pattern may include a top surface having a surface roughness that is smaller than a surface roughness of the top surface of the metal pattern. The magnetic tunnel junction pattern may include bottom and top electrodes, a lower magnetic layer and an upper magnetic layer between the top and bottom electrodes, and a tunnel barrier layer between the lower magnetic layer and the upper magnetic layer.

    Method of fabricating semiconductor device
    9.
    发明授权
    Method of fabricating semiconductor device 有权

    公开(公告)号：US10756092B2

    公开(公告)日：2020-08-25

    申请号：US16814387

    申请日：2020-03-10

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jonghyuk Park ,  Byoungho Kwon ,  Inho Kim ,  Hyesung Park ,  Jin-Woo Bae ,  Yanghee Lee ,  Inseak Hwang

    IPC分类号： H01L27/108 ,  H01L21/66

    摘要： A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion.