公开(公告)号：US20240359286A1

公开(公告)日：2024-10-31

申请号：US18384680

申请日：2023-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon KWON ,  Byoungho Kwon ,  Boun Yoon

IPC: B24B37/04 ,  B24B37/10 ,  B24B37/32

CPC classification number: B24B37/042 ,  B24B37/107 ,  B24B37/32

Abstract: A chemical mechanical polishing apparatus includes a first polishing pad for polishing a substrate, a first polishing head on the first polishing pad to support a substrate, and a second polishing pad spaced apart from the first polishing pad in a horizontal direction. A radius of the second polishing pad is less than a radius of the first polishing pad.

公开(公告)号：US10916554B2

公开(公告)日：2021-02-09

申请号：US16793301

申请日：2020-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Miso Shin ,  Myeongan Kwon ,  Chungki Min ,  Byoungho Kwon ,  Boun Yoon

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.

公开(公告)号：US20190081102A1

公开(公告)日：2019-03-14

申请号：US15919639

申请日：2018-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kichul Park ,  Ki-Woong Kim ,  Hansol Seok ,  Byoungho Kwon ,  Boun Yoon

IPC: H01L27/22 ,  H01L23/522 ,  H01L43/08 ,  H01L43/02 ,  H01F10/32 ,  H01L23/532 ,  H01L23/528 ,  G11C11/16 ,  H01L43/12 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3213

Abstract: A semiconductor memory device may include a selection transistor on a semiconductor substrate, an interlayered insulating layer covering the selection transistor, a lower contact plug coupled to a drain region of the selection transistor and configured to penetrate the interlayered insulating layer, and a magnetic tunnel junction pattern coupled to the lower contact plug. The lower contact plug may include a metal pattern and a capping metal pattern in contact with a top surface of the metal pattern. The capping metal pattern may include a top surface having a surface roughness that is smaller than a surface roughness of the top surface of the metal pattern. The magnetic tunnel junction pattern may include bottom and top electrodes, a lower magnetic layer and an upper magnetic layer between the top and bottom electrodes, and a tunnel barrier layer between the lower magnetic layer and the upper magnetic layer.

公开(公告)号：US09165759B2

公开(公告)日：2015-10-20

申请号：US14086426

申请日：2013-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Won Bae ,  Yongsun Ko ,  Byoungho Kwon ,  Bo yun Kim ,  Hongjin Kim ,  Sungoh Park ,  Kuntack Lee ,  Hyosan Lee ,  Sol Han

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768

CPC classification number: C09K13/06 ,  C23F1/26 ,  H01L21/02074 ,  H01L21/32134 ,  H01L21/76865 ,  H01L21/76883

Abstract: An etching composition includes about 1 wt % to about 7 wt % of hydrogen peroxide, about 20 wt % to about 80 wt % of phosphoric acid, about 0.001 wt % to about 1 wt % of an amine or amide polymer, 0 wt % to about 55 wt % of sulfuric acid, and about 10 wt % to about 45 wt % of deionized water.

Abstract translation: 蚀刻组合物包含约1重量％至约7重量％的过氧化氢，约20重量％至约80重量％的磷酸，约0.001重量％至约1重量％的胺或酰胺聚合物，0重量％ 约55重量％的硫酸和约10重量％至约45重量％的去离子水。

公开(公告)号：US11471996B2

公开(公告)日：2022-10-18

申请号：US16662439

申请日：2019-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchul Han ,  Yonghee Lee ,  Taemin Earmme ,  Byoungho Kwon ,  Kuntack Lee

IPC: B24B37/005 ,  B24B37/20

Abstract: A conditioner of a chemical mechanical polishing (CMP) apparatus includes a disk to polish a polishing pad of the CMP apparatus, a driver to rotate the disk, a lifter to lift the driver, an arm to rotate the lifter, and a connector to connect the driver to the lifter, the driver being tiltable with respect to the lifter.

公开(公告)号：US10716755B2

公开(公告)日：2020-07-21

申请号：US16237913

申请日：2019-01-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbeom Pyon ,  Kichul Park ,  Inkwon Kim ,  Ki Hoon Jang ,  Byoungho Kwon ,  Sangkyun Kim ,  Boun Yoon

IPC: H01L27/112 ,  H01L23/535 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11551 ,  H01L27/11578 ,  H01L21/02 ,  H01L23/538 ,  A61K9/06 ,  A61K45/06 ,  A61K9/00 ,  A61K31/197 ,  A61K47/10 ,  A61K47/12 ,  A61K47/20 ,  A61K47/32 ,  A61K47/44

Abstract: A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.

公开(公告)号：US09677002B2

公开(公告)日：2017-06-13

申请号：US14879835

申请日：2015-10-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Won Bae ,  Yongsun Ko ,  Byoungho Kwon ,  Bo yun Kim ,  Hongjin Kim ,  Sungoh Park ,  Kuntack Lee ,  Hyosan Lee ,  Sol Han

IPC: C09K13/06 ,  C23F1/26 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3213

CPC classification number: C09K13/06 ,  C23F1/26 ,  H01L21/02074 ,  H01L21/32134 ,  H01L21/76865 ,  H01L21/76883

Abstract: An etching composition includes about 1 wt % to about 7 wt % of hydrogen peroxide, about 20 wt % to about 80 wt % of phosphoric acid, about 0.001 wt % to about 1 wt % of an amine or amide polymer, 0 wt % to about 55 wt % of sulfuric acid, and about 10 wt % to about 45 wt % of deionized water.

公开(公告)号：US11322346B2

公开(公告)日：2022-05-03

申请号：US17336924

申请日：2021-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongbong Park ,  Jisu Kim ,  Byoungho Kwon

IPC: H01L21/02 ,  H01L21/306 ,  B08B3/02 ,  B08B3/08 ,  B05B1/14 ,  B08B1/00 ,  B08B1/04 ,  B08B1/02 ,  B24B37/34 ,  B08B3/04

Abstract: A method of processing a substrate may include preparing the substrate, polishing the substrate, and cleaning the substrate using a double nozzle, which is configured to provide a spray and a chemical solution onto the substrate. The spray may include a deionized water, and the chemical solution may be diluted with the deionized water. The chemical solution and the spray may be spaced apart from each other by a distance of 7 cm to 12 cm.

公开(公告)号：US10756092B2

公开(公告)日：2020-08-25

申请号：US16814387

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghyuk Park ,  Byoungho Kwon ,  Inho Kim ,  Hyesung Park ,  Jin-Woo Bae ,  Yanghee Lee ,  Inseak Hwang

IPC: H01L27/108 ,  H01L21/66

Abstract: A method of fabricating a semiconductor device includes providing a substrate including a pair of first regions and a second region therebetween, forming first patterns on the respective first regions to at least partially define a stepwise portion at the second region, and forming a dummy pattern that at least partially fills the stepwise portion. The dummy pattern may be an electrically floating structure. The dummy pattern may be formed as part of forming second patterns on the respective first regions, and the dummy pattern and the second patterns may include substantially common materials. Because the dummy pattern at least partially fills the stepwise portion at the second region, the material layer covering the second patterns and the dummy pattern may omit a corresponding stepwise portion.

公开(公告)号：US10566338B2

公开(公告)日：2020-02-18

申请号：US15922186

申请日：2018-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Miso Shin ,  Myeongan Kwon ,  Chungki Min ,  Byoungho Kwon ,  Boun Yoon

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.