公开(公告)号：US09405260B2

公开(公告)日：2016-08-02

申请号：US13912624

申请日：2013-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-hoon Choi ,  Hyun-soo Kim

IPC: G03G15/00 ,  F16D11/14 ,  F16D41/22

CPC classification number: G03G15/757 ,  F16D11/14 ,  F16D41/22 ,  G03G15/70

Abstract: A power transmitting apparatus includes a driving source, a driving member rotated by the driving source, a driven member linked with the driving member to rotate, a transmitting member disposed between the driving member and the driven member, the transmitting member being rotated by the driving member, axially moved along a rotation direction of the driving member so that the transmitting member is connected to the driven member, and an elastic member disposed between the transmitting member and the driven member, the elastic member providing an elastic bias into the transmitting member so that the transmitting member is separated from the driven member.

Abstract translation: 动力传递装置包括驱动源，由驱动源旋转的驱动构件，与驱动构件连接以旋转的从动构件，设置在驱动构件和从动构件之间的传动构件，传动构件通过驱动旋转 构件沿着所述驱动构件的旋转方向轴向移动，使得所述传递构件连接到所述从动构件，并且弹性构件设置在所述传递构件和所述从动构件之间，所述弹性构件向所述传递构件提供弹性偏置， 传动构件与被驱动构件分离。

公开(公告)号：US20140032984A1

公开(公告)日：2014-01-30

申请号：US13800605

申请日：2013-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-kuk Lee ,  Sang-seok Kang ,  Woo-seop Kim ,  Hyun-soo Kim

IPC: G11C29/08

CPC classification number: G11C29/08 ,  G11C5/04 ,  G11C7/22 ,  G11C11/40 ,  G11C11/4096 ,  G11C29/14 ,  G11C29/56 ,  G11C2029/0401 ,  G11C2029/0407

Abstract: A memory module includes a first rank, a second rank and a test control unit. The first rank includes a plurality of semiconductor memory devices configured to operate in response to a first chip selection signal. The second rank includes a plurality of semiconductor memory devices configured to operate in response to a second chip selection signal. The test control unit is configured to simultaneously enable the first and second chip selection signals to test the first and second ranks in a test mode.

Abstract translation: 存储模块包括第一等级，第二等级和测试控制单元。 第一级包括被配置为响应于第一芯片选择信号而工作的多个半导体存储器件。 第二级包括被配置为响应于第二芯片选择信号而工作的多个半导体存储器件。 测试控制单元被配置为在测试模式中同时使得第一和第二芯片选择信号能够测试第一和第二等级。

公开(公告)号：US09067735B2

公开(公告)日：2015-06-30

申请号：US13875602

申请日：2013-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-soo Kim

IPC: B65H7/02 ,  B65G13/06 ,  B65H3/52

CPC classification number: B65G13/06 ,  B65H3/5261 ,  B65H2403/42 ,  B65H2403/732 ,  B65H2801/09

Abstract: A paper feeding apparatus includes a transfer roller that provides a transfer force of a first direction onto the upper surface of a recording medium; a retard roller that faces the transfer roller to form a transfer nip and provides a transfer force of a second direction opposite to the first direction onto the lower surface of the recording medium; a driving unit that drives the retard roller; and a power delivery unit that connects the driving unit to the retard roller by using a magnetic force and provides a magnetic driving force that is smaller than the transfer force provided by the transfer roller when one recording medium exists in the transfer nip and is larger than a frictional force between two or more recording media when the two or more recording media exist in the transfer nip.

Abstract translation: 送纸装置包括转印辊，其将第一方向的转印力提供到记录介质的上表面上; 面向转印辊以形成转印辊隙的延迟辊，并将与第一方向相反的第二方向的转印力提供到记录介质的下表面上; 驱动所述延迟辊的驱动单元; 以及动力输送单元，其通过使用磁力将驱动单元连接到延迟辊，并且当在转印辊隙中存在一个记录介质时提供小于由转印辊提供的转印力的磁力驱动力，并且大于 当转印辊隙中存在两个或更多个记录介质时，两个或更多个记录介质之间的摩擦力。

公开(公告)号：US10910367B2

公开(公告)日：2021-02-02

申请号：US16257464

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seul-ki Hong ,  Hwi-chan Jun ,  Hyun-soo Kim ,  Dae-chul Ahn ,  Myung Yang

IPC: H01L27/07 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/768 ,  H01L23/31 ,  H01L49/02 ,  H01L29/06

Abstract: A semiconductor device includes a substrate including a first region and a second region, an active gate structure on the substrate in the first region, a dummy gate structure on the substrate in the second region, a source/drain on the substrate in the first region at each of opposite sides of the active gate structure, a plurality of first conductive contacts respectively connected to the active gate structure and the source/drain, a resistive structure on the dummy gate structure in the second region, a plurality of second conductive contacts respectively connected to the plurality of first conductive contacts and the resistive structure, and an etch stop layer between the dummy gate structure and the resistive structure. The etch stop layer includes a lower etch stop layer and an upper etch stop layer, which are formed of different materials.

公开(公告)号：US09026870B2

公开(公告)日：2015-05-05

申请号：US13800605

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-kuk Lee ,  Sang-seok Kang ,  Woo-seop Kim ,  Hyun-soo Kim

IPC: G11C29/00 ,  G11C29/08 ,  G11C29/56 ,  G11C29/14 ,  G11C7/22 ,  G11C11/4096 ,  G11C5/04 ,  G11C11/40 ,  G11C29/04

CPC classification number: G11C29/08 ,  G11C5/04 ,  G11C7/22 ,  G11C11/40 ,  G11C11/4096 ,  G11C29/14 ,  G11C29/56 ,  G11C2029/0401 ,  G11C2029/0407

Abstract: A memory module includes a first rank, a second rank and a test control unit. The first rank includes a plurality of semiconductor memory devices configured to operate in response to a first chip selection signal. The second rank includes a plurality of semiconductor memory devices configured to operate in response to a second chip selection signal. The test control unit is configured to simultaneously enable the first and second chip selection signals to test the first and second ranks in a test mode.

Abstract translation: 存储模块包括第一等级，第二等级和测试控制单元。 第一级包括被配置为响应于第一芯片选择信号而工作的多个半导体存储器件。 第二级包括被配置为响应于第二芯片选择信号而工作的多个半导体存储器件。 测试控制单元被配置为在测试模式中同时使得第一和第二芯片选择信号能够测试第一和第二等级。