公开(公告)号：US20240203466A1

公开(公告)日：2024-06-20

申请号：US18230776

申请日：2023-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyoung PARK ,  Garam KIM ,  Joohwan KIM ,  Jindo BYUN ,  Eunseok SHIN ,  Hyunyoon CHO ,  Junghwan CHOI

IPC: G11C7/10 ,  H03K19/017

CPC classification number: G11C7/1066 ,  G11C7/1063 ,  H03K19/01742

Abstract: A transmitter configured to receive first to N-th data in parallel and sequentially output the first to N-th data in response to first to N-th clock signals having different phases from each other, where N is an integer of at least 2, the transmitter including first to N-th data selectors including a first data selector and a second data selector in correspondence to the first to N-th data, each of the first to N-th data selectors being configured to perform a logical operation on one of the first to N-th data and the first to N-th clock signals and output a plurality of data selection signals, a first pre-driver in correspondence to at least two data selectors among the first to N-th data selectors, the first pre-driver being configured to receive the plurality of data selection signals from the at least two data selectors.

公开(公告)号：US20230116188A1

公开(公告)日：2023-04-13

申请号：US17943448

申请日：2022-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsub RIE ,  Eunseok SHIN ,  Youngdon CHOI ,  Changsoo YOON ,  Hyunyoon CHO ,  Junghwan CHOI

IPC: G11C11/4096 ,  H03M1/12

Abstract: A receiver receiving a multi-level signal includes a sample and hold circuit, first and second analog-to-digital converting circuits, and a digital-to-analog converting circuit. The sample and hold circuit generates a sample data signal by sampling and holding an input data signal. The first analog-to-digital converting circuit generates a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages. The digital-to-analog converting circuit selects at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data. The second analog-to-digital converting circuit generates at least one additional bit of the output data based on the sample data signal and the at least one additional selection reference voltage.

公开(公告)号：US20220404852A1

公开(公告)日：2022-12-22

申请号：US17577201

申请日：2022-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woochul JUNG ,  Myoungbo KWAK ,  Jaewoo PARK ,  Eunseok SHIN ,  Junhan CHOI

IPC: G05F1/575 ,  G11C5/14 ,  G11C8/18 ,  G11C8/10

Abstract: A voltage regulator and a semiconductor memory device having the same are disclosed. The voltage regulator includes an amplifier configured to amplify a difference between a reference voltage and a feedback voltage to generate an amplifier output voltage, a voltage feedback unit connected between an output supply voltage generation node and a ground voltage and configured to generate the feedback voltage, a first transfer gate unit connected between an input supply voltage and the voltage generation node and driven in response to the amplifier output voltage to provide first current, a current load replica unit connected between the voltage generation node and the ground voltage and configured to consume the first current, and a transfer unit connected between the input supply voltage and the voltage generation node and driven in response to the amplifier output voltage when the current load unit performs an operation, to provide second current.

公开(公告)号：US20230185754A1

公开(公告)日：2023-06-15

申请号：US17899883

申请日：2022-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok SHIN ,  Woochul JUNG ,  Jungho KO ,  Myoungbo KWAK ,  Jaewoo PARK ,  Sunjae LIM ,  Junghwan CHOI

IPC: G06F13/42 ,  H03M9/00

CPC classification number: G06F13/4204 ,  H03M9/00 ,  G06F13/4282 ,  H03K17/6871

Abstract: A parallel-to-serial interface circuit includes an equalizer to delay odd data by a half period and sequentially generate odd pre data, odd main data, and odd post data, and delay even data by a half period and sequentially generate even pre data, even main data, and even post data, a final parallel-to-serial converter to sequentially and alternately select the even pre data and the odd pre data to generate pre data, sequentially and alternately select inverted odd main data and inverted even main data to generate inverted main data, and sequentially and alternately select the even post data and the odd post data to generate post data, and a driver to drive the pre data to generate a pre data level, drive the inverted main data to generate an inverted main data level, and drive the post data to generate a post data level.

公开(公告)号：US20240187002A1

公开(公告)日：2024-06-06

申请号：US18350606

申请日：2023-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwook LEE ,  Joohwan KIM ,  Junyoung PARK ,  Jindo BYUN ,  Eunseok SHIN ,  Junghwan CHOI

IPC: H03L7/081 ,  G11C7/22 ,  H03K5/135

CPC classification number: H03L7/0812 ,  G11C7/222 ,  H03K5/135

Abstract: A semiconductor device includes a phase splitter configured to output a plurality of clock signals having different phases by using a plurality of external clock signals having different phases, a plurality of code generators configured to receive a pair of selection clock signals determined from the plurality of clock signals and to output a phase code corresponding to a phase difference error between the pair of selection clock signals, and a delay circuit configured to at least partly simultaneously adjust at least two of a rising edge and a falling edge of each of the plurality of external clock signals with reference to the phase code during a lock time.

公开(公告)号：US20220385287A1

公开(公告)日：2022-12-01

申请号：US17751148

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung PARK ,  Joohwan KIM ,  Jindo BYUN ,  Eunseok SHIN ,  Hyunyoon CHO ,  Youngdon CHOI ,  Junghwan CHOI

IPC: H03K17/693 ,  H03K19/20

Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.