公开(公告)号：US20240145474A1

公开(公告)日：2024-05-02

申请号：US18314484

申请日：2023-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung ho KIM ,  Myung Il KANG ,  Sung Uk JANG ,  Kyung Hee CHO ,  Do Young CHOI

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes a substrate, a first active pattern disposed on the substrate, a second active pattern stacked on the first active pattern, a first gate structure extending to intersect the first active pattern and the second active pattern, a second gate structure spaced apart from the first gate structure and extending to intersect the first active pattern and the second active pattern, a first epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the first active pattern, a second epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the second active pattern, an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern, and a semiconductor film interposed between the insulating pattern and the second epitaxial pattern, the semiconductor film extending along a top surface of the insulating pattern.

公开(公告)号：US20240357787A1

公开(公告)日：2024-10-24

申请号：US18540008

申请日：2023-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchan HWANG ,  Kyung Hee CHO ,  Seunghun LEE

IPC: H10B10/00 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423

CPC classification number: H10B10/12 ,  H01L23/5226 ,  H01L23/5286 ,  H01L29/4232

Abstract: A semiconductor memory device comprising a substrate having first and second surfaces opposite to each other, a lower active region on the first surface and including a first lower gate electrode and a first lower active contact, an upper active region on the lower active region and including a first upper gate electrode and a first upper active contact that vertically overlap at least a part of the first lower active contact, a first connection structure vertically connecting the first upper active contact to the first lower active contact, a first metal layer on the first surface, and a backside metal layer on the second surface. The first upper gate electrode and the first lower gate electrode are connected and form a first gate electrode. The first metal layer includes a first node line electrically connecting the first gate electrode to the first upper active contact.

公开(公告)号：US20240113110A1

公开(公告)日：2024-04-04

申请号：US18199014

申请日：2023-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Hee CHO ,  Seokhyeon YOON ,  Hyeongrae KIM ,  Jeewoong SHIN

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes first and second active patterns on first and second PMOS regions, two first source/drain patterns spaced apart along a first direction on the first active pattern and a first channel pattern including first semiconductor patterns between the two first source/drain patterns, and two second source/drain patterns spaced apart along the first direction on the second active pattern and a second channel pattern including second semiconductor patterns between the two second source/drain patterns. A width in a second direction of the each of the first semiconductor patterns is greater than a width of each of the second semiconductor patterns. Each of the first and second source/drain patterns includes semiconductor layers having different germanium concentrations. A number of the semiconductor layers of each of the two second source/drain patterns is greater than a number of the semiconductor layers of each of the two first source/drain patterns.

公开(公告)号：US20250159929A1

公开(公告)日：2025-05-15

申请号：US18756943

申请日：2024-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung-Mi PARK ,  Hyo Jin KIM ,  Dong Hoon HWANG ,  Young Jin YANG ,  Kyung Hee CHO

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device is provided. The semiconductor device includes a first lower pattern extending in a first direction and including first and second sidewalls, which are opposite to each other in a second direction, and upper and lower surfaces, which are opposite to each other in a third direction, a channel separation structure extending in the first direction and contacting the first sidewall of the first lower pattern, a field insulating film contacting the second sidewall of the first lower pattern, first channel patterns disposed on an upper surface of the first lower pattern and including first sheet patterns, which are spaced apart from one another in the third direction, the first sheet patterns contacting the channel separation structure, first source/drain patterns contacting the first channel patterns and the channel separation structure, contact blocking patterns disposed on the first source/drain patterns and formed of an insulating material, the contact blocking patterns having upper surfaces on the same plane as an upper surface of the channel separation structure, first backside source/drain contacts disposed within the first lower pattern and connected to the first source/drain patterns and backside wiring lines disposed on the lower surface of the first lower pattern and connected to the first backside source/drain contacts.

公开(公告)号：US20230389257A1

公开(公告)日：2023-11-30

申请号：US18076963

申请日：2022-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min SONG ,  Hyo-Jin KIM ,  Kyung Hee CHO

IPC: H01L27/11

CPC classification number: H01L27/1108

Abstract: A semiconductor device includes a substrate, a lower active pattern which is spaced apart from the substrate and extends in a first direction, an upper active pattern on the lower active pattern, the upper active pattern being spaced apart from the lower active pattern and extending in the first direction, a gate structure on the substrate, the gate structure extending in a second direction intersecting the first direction, and a cutting pattern on the substrate, the cutting pattern extending in the first direction to cut the gate structure. The gate structure includes a lower gate electrode through which the lower active pattern penetrates, an upper gate electrode which is connected to the lower gate electrode and through which the upper active pattern penetrates, and an insulating pattern on one side of the cutting pattern, the insulating pattern being arranged with the upper gate electrode along the second direction.

公开(公告)号：US20250081599A1

公开(公告)日：2025-03-06

申请号：US18616279

申请日：2024-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hoon HWANG ,  Hyo Jin KIM ,  Byung Ho MOON ,  Kyoung-MI PARK ,  Kyung Hee CHO

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device that includes a lower pattern extending in a first direction, a first channel pattern on the lower pattern, and includes a plurality of first sheet patterns, a second channel pattern on the lower pattern, includes a plurality of second sheet patterns and spaced apart from the first channel pattern, a first gate structure which extends around the first sheet pattern, and includes a first gate electrode and a first gate insulating film, a second gate structure which extends around the second sheet pattern, and includes a second gate electrode and a second gate insulating film, a first gate capping pattern and a second gate capping pattern. The number of first sheet patterns is different from the number of second sheet patterns, and a thickness of the first gate capping pattern is different from a thickness of the second gate capping pattern.

公开(公告)号：US20240105724A1

公开(公告)日：2024-03-28

申请号：US18196741

申请日：2023-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHOON HWANG ,  MYUNGIL KANG ,  MINCHAN GWAK ,  Kyungho KIM ,  Kyung Hee CHO ,  DOYOUNG CHOI

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A three-dimensional semiconductor device includes a first active region on a substrate, the first active region including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region stacked on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a lower contact electrically connected to the lower source/drain pattern, the lower contact having a bar shape extending on the lower source/drain pattern in a first direction, a first active contact coupled to the lower contact, and a second active contact coupled to the upper source/drain pattern. A first width of the lower source/drain pattern in a second direction is larger than a second width of the lower contact in the second direction.