Abstract:
An image sensor includes: a top layer including a photodiode included in a pixel and a transfer transistor configured to transfer an electrical signal generated by the photodiode; a first middle layer under the top layer and bonded to the top layer, wherein the first middle layer includes a plurality of capacitors connected to the transfer transistor through a first output node connected to the transfer transistor, and a plurality of sampling transistors connected to the plurality of capacitors and configured to control the plurality of capacitors; a second middle layer under the first middle layer and bonded to the first middle layer, wherein the second middle layer includes a source-follow transistor connected to the plurality of sampling transistors through a second output node; and a bottom layer under the second middle layer and bonded to the second middle layer, wherein the bottom layer includes an analog-to-digital converter (ADC) circuit configured to process a pixel signal output through the source-follow transistor.
Abstract:
Provided is an image sensor including a semiconductor substrate having first and second surfaces, transistors on the first surface, first and second lower pad electrodes apart from each other on a first interlayer insulating film covering the transistors, a mold insulating layer on the first and second lower pad electrodes, a first lower electrode inside a first opening passing through the mold insulating layer on the first lower pad electrode, a second lower electrode inside a second opening passing through the mold insulating layer on the second lower pad electrode, a dielectric film and an upper electrode on the first and second lower electrodes, a first contact plug passing through the mold insulating layer and connected to the first lower pad electrode, and a second contact plug passing through the mold insulating layer and connected to the second lower pad electrode.
Abstract:
An imaging device includes a pixel array with first and second pixels respectively having first and second conversion gains connected to row and column lines; a row driver determining a selection row line among the row lines; a readout circuit obtaining first and second pixel signals from first and second pixels connected to the selection row line; a column driver generating first and second image data from the first and second pixel signals; and an image signal processor using the first and second image data to generate an object image. The second pixels include an expansion capacitor connected between a floating diffusion node and a ground node. Exposure time of the first pixels is equal to or longer than exposure time of the second pixels. An area of a light receiving region of the first pixels is equal to an area of a light receiving region of the second pixels.
Abstract:
Disclosed is an image sensor comprising a first substrate including a plurality of pixels, a photoelectric conversion region in the first substrate at each of the pixels, a first capacitor on the first substrate, and a shield structure spaced apart from and surrounding the first capacitor.
Abstract:
An image sensor is provided. The image sensor includes a first substrate; a plurality of photoelectric conversion units positioned in the first substrate; a first connection layer disposed on the first substrate; a plurality of first pixel pads disposed on the first connection layer; a plurality of first peripheral pads disposed on the first substrate; a plurality of second pixel pads respectively positioned on the plurality of first pixel pads; a plurality of second peripheral pads respectively positioned on the plurality of first peripheral pads; a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads; a device disposed on the second connection layer; and a second substrate disposed on the second connection layer and the device, wherein a pitch of the plurality of first pixel pads is substantially the same as a pitch of the plurality of pixel regions of the first substrate.
Abstract:
Resistive memory driving methods are provided. The methods may include applying an operating voltage set according to a mode of operation to a selected word line among the plurality of word lines and a selected bit line among the plurality of bit lines within a line delay period.
Abstract:
An image sensor includes a lower insulating film arranged over a substrate and having a non-flat surface that has a concave-convex shape and includes a first surface, which extends in a horizontal direction parallel to a frontside surface of the substrate, and at least one second surface extending from the first surface toward the substrate, a capacitor arranged on the lower insulating film to contact the non-flat surface of the lower insulating film and conformally covering the non-flat surface of the lower insulating film along the contour of the non-flat surface of the lower insulating film, an upper insulating film covering the capacitor and the lower insulating film, and at least one air gap having a side facing the at least one second surface of the lower insulating film in the horizontal direction and having a height defined by the upper insulating film in a vertical direction.
Abstract:
An image sensor may include a substrate including pixels, a first transistor and a second transistor disposed on the substrate and spaced apart from each other, a first interlayer insulating layer covering the first transistor and the second transistor, a first lower electrode disposed in the first interlayer insulating layer and connected to an end portion of the first transistor, a first dielectric layer on the first lower electrode, a first upper electrode on the first dielectric layer, a second interlayer insulating layer covering the first upper electrode and the first interlayer insulating layer, and a first pillar provided to penetrate the second and first interlayer insulating layers and connected to an end portion of the second transistor.
Abstract:
An image sensor includes a first layer including pixels in a pixel array, and a first logic circuit configured to control the pixel array. Each of the pixels include at least one photodiode configured to generate a charge in response to light, and a pixel circuit configured to generate a pixel signal corresponding to the charge. A second layer includes a second logic circuit that is connected to the pixel array and the first logic circuit and is on the first layer. A third layer includes storage elements that are electrically connected to at least one of the pixels or the first logic circuit and an insulating layer on the storage elements. A lower surface of the insulating layer is attached to an upper portion of the first layer, and an upper surface of the insulating layer is attached to a lower portion of the second layer.
Abstract:
A method of operating a resistive non-volatile memory can be provided by applying a forming voltage across first and second electrodes of a selected memory cell in the variable resistance non-volatile memory device during an operation to the selected memory cell. The forming voltage can be a voltage level that is limited to less than a breakdown voltage of an insulation film included in selected memory cell between a variable resistance film and one of first electrode. Related devices and materials are also disclosed.