公开(公告)号：US20240162193A1

公开(公告)日：2024-05-16

申请号：US18213852

申请日：2023-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongyo KIM ,  UN-BYOUNG KANG ,  SANG-SICK PARK ,  Hanmin LEE ,  Seungyoon JUNG

IPC: H01L25/065 ,  B23K26/38 ,  B23K26/40 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/0657 ,  B23K26/38 ,  B23K26/40 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  B23K2101/40 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first semiconductor chip, a lower adhesion layer on the first semiconductor chip, a second semiconductor chip on the lower adhesion layer, an upper adhesion layer on the second semiconductor chip, and a third semiconductor chip on the upper adhesion layer. The lower adhesion layer includes a first cutting surface connected to a top surface of the lower adhesion layer. The upper adhesion layer is in contact with the first cutting surface of the lower adhesion layer.

公开(公告)号：US20230230946A1

公开(公告)日：2023-07-20

申请号：US17939127

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongyo KIM ,  UN-BYOUNG KANG ,  MINSOO KIM ,  SANG-SICK PARK ,  Seungyoon JUNG

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/08 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/81203 ,  H01L24/81 ,  H01L2924/3511 ,  H01L2924/182 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2224/17104 ,  H01L2224/17179 ,  H01L2224/17132 ,  H01L2224/16012 ,  H01L2224/16055 ,  H01L2224/16059 ,  H01L2224/16104 ,  H01L2224/0801 ,  H01L2224/08056 ,  H01L2224/08055 ,  H01L2224/0903 ,  H01L2224/09179 ,  H01L2224/09132 ,  H01L2224/73204

Abstract: A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region. Each of the connection terminals may include a convex portion at a lateral surface thereof, which protrudes beyond a lateral surface of a respective first pad and a lateral surface of a respective second pad. The convex portion may protrude in a direction away from a center of the first die. Protruding distances of the convex portions may increase in a direction from the center of the first die toward an outside of the first die.

公开(公告)号：US20240429205A1

公开(公告)日：2024-12-26

申请号：US18826592

申请日：2024-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANG-SICK PARK ,  UN-BYOUNG KANG ,  JONGHO LEE ,  TEAK HOON LEE

IPC: H01L25/065 ,  H01L23/00

Abstract: Disclosed is a semiconductor package with increased thermal radiation efficiency, which includes: a first die having signal and dummy regions and including first vias in the signal region, a second die on the first die and including second vias in the signal region, first die pads on a top surface of the first die and coupled to the first vias, first connection terminals on the first die pads which couple the second vias to the first vias, second die pads in the dummy region and on the top surface of the first die, and second connection terminals on the second die pads and electrically insulated from the first vias and the second vias. Each of the second die pads has a rectangular planar shape whose major axis is provided along a direction that leads away from the signal region.

公开(公告)号：US20230207533A1

公开(公告)日：2023-06-29

申请号：US18182246

申请日：2023-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HWAN HWANG ,  SANG-SICK PARK ,  TAE-HONG MIN ,  GEOL NAM

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/0655 ,  H01L25/105 ,  H01L24/73 ,  H01L24/32 ,  H01L24/92 ,  H01L24/17 ,  H01L25/50 ,  H01L2225/06586 ,  H01L23/3128

Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

公开(公告)号：US20170243857A1

公开(公告)日：2017-08-24

申请号：US15439321

申请日：2017-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HWAN HWANG ,  SANG-SICK PARK ,  TAE-HONG MIN ,  GEOL NAM

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/8385 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058

Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

公开(公告)号：US20250070072A1

公开(公告)日：2025-02-27

申请号：US18640576

申请日：2024-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongyo KIM ,  MINSOO KIM ,  SANG-SICK PARK

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor die, a first under-fill layer on an upper surface of the first semiconductor die, a second under-fill layer on the first under-fill layer, a second semiconductor die provided on the second under-fill layer, and a mold layer on side surfaces of the second semiconductor die, the second under-fill layer, and the upper surface of the first semiconductor die. The first semiconductor die includes a first substrate, a first redistribution pattern on the first substrate, a first redistribution dielectric layer provided on the first redistribution pattern, and a first dam on the first redistribution dielectric layer and along an edge of the first substrate, and the first under-fill layer contacts a side surface of the first dam.

公开(公告)号：US20240170449A1

公开(公告)日：2024-05-23

申请号：US18213018

申请日：2023-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOUNGJOO LEE ,  SANG-SICK PARK ,  CHUNGSUN LEE ,  SEUNGYOON JUNG

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/83 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0801 ,  H01L2224/0903 ,  H01L2224/09517 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81097 ,  H01L2224/81203 ,  H01L2224/83097 ,  H01L2224/83203 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/351

Abstract: A method includes providing a first structure, forming a connection pad on the first structure, forming a preliminary connection member on the connection pad, forming an adhesion layer on the first structure, the adhesion layer covering the preliminary connection member, removing a portion of the adhesion layer to expose an exposure surface of the preliminary connection member, providing a second structure, forming a chip pad and a dummy pad on the second structure, and covering the chip pad and the dummy pad with the adhesion layer that has been formed on the first structure. A thickness of the dummy pad is greater than a thickness of the chip pad.

公开(公告)号：US20210280564A1

公开(公告)日：2021-09-09

申请号：US17329036

申请日：2021-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HWAN HWANG ,  SANG-SICK PARK ,  TAE-HONG MIN ,  GEOL NAM

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

公开(公告)号：US20240145437A1

公开(公告)日：2024-05-02

申请号：US18409778

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HWAN HWANG ,  SANG-SICK PARK ,  TAE-HONG MIN ,  GEOL NAM

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L23/3128 ,  H01L2225/06586

Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

公开(公告)号：US20220285321A1

公开(公告)日：2022-09-08

申请号：US17664565

申请日：2022-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANG-SICK PARK ,  MIN SOO KIM

IPC: H01L25/065

Abstract: A semiconductor package includes a base substrate having a first semiconductor substrate, and a first protective layer covering a top side thereof. A first semiconductor chip is on the first protective layer. A first fillet layer fills a space between the first protective layer and the first semiconductor chip. A first side surface of the base substrate extends in a first direction, and second and third side surfaces extend in a second direction. The base substrate includes two corner regions and a side region between the corner regions. A first protective layer in the side region includes a first side trench which overlaps the first semiconductor chip. A part of the first fillet layer fills the first side trench.