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公开(公告)号:US09379122B2
公开(公告)日:2016-06-28
申请号:US14600577
申请日:2015-01-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jin-Hyun Shin , Jae-Bok Baek
IPC: H01L27/115 , H01L29/788 , H01L29/06 , H01L21/764 , G11C5/06 , G11C16/04
CPC classification number: H01L27/11524 , G11C5/063 , G11C16/0483 , H01L21/764 , H01L29/0649 , H01L29/7883
Abstract: A memory device includes an array of floating gate memory cells. Adjacent memory cells are separated by a plurality of air gaps that electrically decouple respective active regions of adjacent memory cells from one another. Additionally, the air gaps electrically decouple an active region of a memory cell from a floating gate of an adjacent memory cell.
Abstract translation: 存储器件包括浮动栅极存储器单元阵列。 相邻的存储器单元被多个气隙隔开,这些气隙将相邻存储器单元的相应有源区彼此电分离。 此外,气隙将存储器单元的有源区域与相邻存储单元的浮动栅极电耦合。
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公开(公告)号:US20250126801A1
公开(公告)日:2025-04-17
申请号:US18732848
申请日:2024-06-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Ju Seong Min , Hak Seon Kim , Jae-Bok Baek , Kang-Oh Yun , Taek Kyu Yoon , Dong Jin Lee , Jae Duk Lee , Se Jin Lim , Jee Hoon Han
Abstract: The present disclosure relates to semiconductor memory devices. An example semiconductor memory device includes a cell region and a peripheral circuit region electrically connected with the cell region. The cell region includes a plurality of gate electrodes spaced apart from each other and stacked in a vertical direction, and a channel structure extending through the plurality of gate electrodes in the vertical direction. The peripheral circuit region includes a substrate, a first element isolation structure, a first gate structure on the first active region, a second element isolation structure, a second gate structure on the second active region, a third element isolation structure, and a third gate structure on the third active region. The third element isolation structure includes a first element isolation pattern and a second element isolation pattern. The first element isolation pattern and the second element isolation pattern include different materials from each other.
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公开(公告)号:US20250107098A1
公开(公告)日:2025-03-27
申请号:US18807157
申请日:2024-08-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kohji Kanamori , Jae-Bok Baek , Donghyuck Jang , Jeehoon Han
Abstract: Disclosed are semiconductor devices and electronic systems. The semiconductor device comprises a semiconductor substrate including first and second cell array regions and a connection region including a lower pad region and an upper pad region, a peripheral circuit structure including peripheral circuits on the semiconductor substrate, and a cell array structure on the peripheral circuit structure and including a first stack structure including first conductive patterns stacked on the peripheral circuit structure and a second stack structure including second conductive patterns stacked on the first stack structure. The first stack structure includes a connection portion that has a uniform thickness on the upper pad region, and first and second stepwise structures that are asymmetric with each other on the lower pad region. The second stack structure includes third and fourth stepwise structures that are symmetric with each other on the connection portion of the first stack structure.
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公开(公告)号:US20240162225A1
公开(公告)日:2024-05-16
申请号:US18318854
申请日:2023-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Juseong MIN , Jae-Bok Baek , Taekkyu Yoon , Seungwook Choi , Jeehoon Han , Taeyoon Hong
IPC: H01L27/08 , H01L21/306 , H01L21/308
CPC classification number: H01L27/0802 , H01L21/30604 , H01L21/308 , H01L28/20
Abstract: A semiconductor device includes an active pattern having sharp corners. The semiconductor device includes a peripheral circuit including a substrate, a resistor device in the substrate, and an active pattern on the substrate. When viewed in a plan view, the active pattern includes corners in a serpentine shape, and first and second shapes of the corners are different from each other.
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