公开(公告)号：US20250094680A1

公开(公告)日：2025-03-20

申请号：US18617946

申请日：2024-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyong LEE ,  Jaeyong JEONG

IPC: G06F30/392 ,  G06F30/398 ,  G06F119/18

Abstract: Disclosed is an operating method of an electronic device which includes a processor and supports manufacture of a semiconductor device. The method includes receiving, at the processor, layout data for the manufacture of the semiconductor device, feature data of the layout data, and skew data after the semiconductor device is manufactured; inferring, at the processor, a center and a distribution of a skew of each of patterns and/or edges of the layout data based on the layout data and the feature data, by using a deep learning module; calculating, at the processor, a loss based on the center and the distribution of the skew based on the skew data, and training, at the processor, the deep learning module based on the loss, and the layout data, the feature data, and the skew data are formatted as tabular data.

公开(公告)号：US20130219109A1

公开(公告)日：2013-08-22

申请号：US13755144

申请日：2013-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Bum KIM ,  Jaeyong JEONG ,  Kitae PARK

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F11/1068 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5641

Abstract: A memory system includes a nonvolatile memory device having a first data area storing M-bit data using a buffer program operation and a second data area storing N-bit data (N being an integer larger than M) using a main program operation and a memory controller configured to control the nonvolatile memory device. When a main program operation using data stored at the first and second data areas is required, the memory controller calculates values indicating a performance of the required main program operation to be executed according to a plurality of main program manners, selects one of the plurality of main program manners based on the calculated values, and controls the nonvolatile memory device to perform the required main program operation according to the selected main program manner.

Abstract translation: 存储器系统包括：非易失性存储器件，其具有使用缓冲器程序操作存储M位数据的第一数据区和使用主程序操作存储N位数据（N大于M的整数）的第二数据区;存储器 控制器被配置为控制非易失性存储器件。 当需要使用存储在第一和第二数据区域的数据的主程序操作时，存储器控制器根据多个主程序方式计算指示要执行的所需主程序操作的性能的值，选择多个 基于计算值的主程序方式，并且根据选择的主程序方式控制非易失性存储器件执行所需的主程序操作。

公开(公告)号：US20230395111A1

公开(公告)日：2023-12-07

申请号：US18235189

申请日：2023-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuiyon MUN ,  Beomkyu SHIN ,  Jaeyong JEONG

IPC: G11C8/18 ,  G11C8/06 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C8/06 ,  G11C7/222 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/106 ,  G11C7/1087

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

公开(公告)号：US20220101900A1

公开(公告)日：2022-03-31

申请号：US17549095

申请日：2021-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuiyon MUN ,  Beomkyu SHIN ,  Jaeyong JEONG

IPC: G11C8/18 ,  G11C8/06 ,  G11C7/22 ,  G11C7/10

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

公开(公告)号：US20210026553A1

公开(公告)日：2021-01-28

申请号：US16811682

申请日：2020-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo KIM ,  Jaeyong JEONG ,  Myunghyun JO ,  Wonhee CHO

IPC: G06F3/06

Abstract: A system-on-chip includes a first intellectual property (IP) generating a plurality of request packets; and a second IP generating a plurality of response packets based on the plurality of request packets, wherein the second IP includes a plurality of processing elements processing the plurality of request packets and generating the plurality of response packets; a distributer, when the plurality of request packets are input from the first IP, determining a scheduling policy based on a packet type of the plurality of request packets and distributing the plurality of request packets to the plurality of processing elements according to the determined scheduling policy; and an aggregator, when the plurality of response packets are received from each of the plurality of processing elements, aggregating the plurality of response packets according to the determined scheduling policy.

公开(公告)号：US20180122485A1

公开(公告)日：2018-05-03

申请号：US15625189

申请日：2017-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Soo PARK ,  Jaeyong JEONG

IPC: G11C16/30 ,  G11C16/14 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/30 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/14 ,  G11C16/225 ,  G11C16/24 ,  G11C16/26

Abstract: A nonvolatile memory device includes a memory cell array that stores data, and control logic. The control logic is configured to control a read operation, a program operation, or an erase operation on the data. The control logic is configured to detect a first power noise based on one of voltage sources to be provided to the memory cell array and a first reference voltage and detect a second power noise based on the one voltage source of the voltage sources and each of the first reference voltage and a second reference voltage. The control logic is configured to determine whether to perform at least one of an operation period of the read operation, an operation period of the program operation, or an operation period of the erase operation, based on whether at least one of the first and second power noises is detected.