公开(公告)号：US11950420B2

公开(公告)日：2024-04-02

申请号：US17517220

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Jin Park ,  Sun Young Kim ,  Jang Gn Yun

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L23/528 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/50

Abstract: A memory device includes gate electrode layers stacked on an upper surface of a substrate and each including a plurality of unit electrodes extending in a first direction, and a plurality of connecting electrodes connecting the unit electrodes to each other. The memory device also includes channel structures extending through the gate electrode layers in a direction perpendicular to the upper surface of the substrate, first common source lines extending in the first direction and interposed between the unit electrodes, and second common source lines extending in the first direction between the first common source lines and each having a first line and a second line separated from each other in the first direction by the connecting electrodes.

公开(公告)号：US11574923B2

公开(公告)日：2023-02-07

申请号：US17152883

申请日：2021-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang Gn Yun ,  Jae Duk Lee

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor device includes a stacked structure on a lower structure, the stacked structure including a lower group including gate electrodes vertically stacked and spaced apart from each other, and an upper group including gate electrodes vertically stacked and spaced apart, the lower group and the upper group being vertically stacked, and a vertical structure passing through the stacked structure. The vertical structure may include a vertical core pattern, a vertical buffer portion therein, and a surrounding vertical semiconductor layer, the vertical structure may include a lower vertical portion passing through the lower group and an upper vertical portion passing through the upper group, an upper region of the lower vertical portion may have a width greater than that of a lower region of the upper vertical portion. The vertical buffer portion may be in the lower vertical portion and below the upper vertical portion.

公开(公告)号：US10204901B2

公开(公告)日：2019-02-12

申请号：US15723669

申请日：2017-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Seok Woo ,  Jang Gn Yun ,  Joon Sung Lim ,  Sung Min Hwang

IPC: H01L27/00 ,  H01L27/07 ,  H01L23/00 ,  H01L49/02 ,  H01L29/43 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/49

Abstract: A semiconductor device is provided including a resistor structure on a semiconductor substrate. The resistor structure includes pad portions and a resistor body connecting the pad portions. The pad portions each have a width greater than a width of the resistor body. The pad portions each include a pad pattern and a liner pattern covering a sidewall and a lower surface of the pad pattern. The resistor body extends laterally from the liner pattern. The pad pattern includes a different material from the resistor body and the liner pattern.

公开(公告)号：US10115734B2

公开(公告)日：2018-10-30

申请号：US15398735

申请日：2017-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang Gn Yun ,  Sun Young Kim

IPC: H01L29/792 ,  H01L27/11582 ,  H01L23/528

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes interlayer support patterns sequentially stacked on a substrate, horizontal conductive patterns sequentially stacked on the substrate, and an interlayer insulating layer disposed between the interlayer support patterns, extending between the horizontal conductive patterns, and disposed in parallel with a surface of the substrate. The interlayer insulating layer is in contact with the interlayer support patterns. A conductive structure extends in a direction perpendicular to the substrate. Vertical structures extending through the horizontal conductive patterns and the interlayer insulating layer are formed.

公开(公告)号：US10903234B2

公开(公告)日：2021-01-26

申请号：US16275756

申请日：2019-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang Gn Yun ,  Jae Duk Lee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A three-dimensional semiconductor device includes a stacked structure on a lower structure, the stacked structure including a lower group including gate electrodes vertically stacked and spaced apart from each other, and an upper group including gate electrodes vertically stacked and spaced apart, the lower group and the upper group being vertically stacked, and a vertical structure passing through the stacked structure. The vertical structure may include a vertical core pattern, a vertical buffer portion therein, and a surrounding vertical semiconductor layer, the vertical structure may include a lower vertical portion passing through the lower group and an upper vertical portion passing through the upper group, an upper region of the lower vertical portion may have a width greater than that of a lower region of the upper vertical portion. The vertical buffer portion may be in the lower vertical portion and below the upper vertical portion.

公开(公告)号：US10446580B2

公开(公告)日：2019-10-15

申请号：US16298349

申请日：2019-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang Gn Yun ,  Sun Young Kim ,  Hoo Sung Cho

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/522

Abstract: A memory device includes a pair of common source lines disposed on a substrate spaced apart from each other and extended in a first direction; a plurality of ground select lines disposed between the pair of common source lines, extended in the first direction, and disposed on the same level; a plurality of word lines disposed on the plurality of ground select lines between the pair of common source lines, extended in the first direction, and disposed on the same level, at least a portion of the plurality of word lines being connected by a connection electrode; and a plurality of first separation insulating patterns disposed between individual ground select lines of a portion of the plurality of ground select lines and extended in the first direction. The at least portion of the plurality of word lines is connected by a connection electrode.

公开(公告)号：US09853045B2

公开(公告)日：2017-12-26

申请号：US15173888

申请日：2016-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min Hwang ,  Jang Gn Yun ,  Ahn Sik Moon ,  Se Jun Park ,  Zhiliang Xia ,  Joon Sung Lim

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device includes a gate stack including gate electrodes stacked vertically on a substrate. Channel holes penetrate through the gate stack to extend vertically to the substrate. Each of the channel holes includes a channel region. First channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the first channel pads includes at least one first conductivity-type impurity. Second channel pads are each disposed at an end of a respective channel hole opposite the substrate. Each of the second channel pads includes at least one second conductivity-type impurity.