中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.016 seconds)

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    3.
    发明公开
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230413545A1

    公开(公告)日：2023-12-21

    申请号：US18365915

    申请日：2023-08-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung Min Hwang ,  Joon Sung Lim ,  Bum Kyu Kang ,  Jae Ho Ahn

    IPC: H10B41/27 ,  H01L23/535

    CPC classification number: H10B41/27 ,  G11C16/0483 ,  H01L23/535

    Abstract: A three-dimensional semiconductor device includes a first gate group on a lower structure and a second gate group on the first gate group. The first gate group includes first pad regions that are: (1) lowered in a first direction that is parallel to an upper surface of the lower structure and (2) raised in a second direction that is parallel to an upper surface of the lower structure and perpendicular to the first direction. The second gate group includes second pad regions that are sequentially raised in the first direction and raised in the second direction.

    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    4.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190312054A1

    公开(公告)日：2019-10-10

    申请号：US16239130

    申请日：2019-01-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jang Gn YUN ,  Joon Sung Lim ,  Eun Suk Cho

    IPC: H01L27/11582 ,  H01L27/11565

    Abstract: A three-dimensional semiconductor device and method of fabrication is provided. The three-dimensional semiconductor device includes a stacked structure on a lower structure. The stacked structure includes interlayer insulating layers and gate electrodes. The device also includes a channel structure on the lower structure, with the channel structure including a horizontal portion between the stacked structure and the lower structure. The channel structure also includes a plurality of vertical portions extended in a vertical direction. The device also includes support patterns on the lower structure. In addition, the device includes a gate dielectric structure having a lower portion and upper portions. The method of fabrication includes forming the stacked structure with holes. The method also includes removing a sacrificial layer from a horizontal area above the lower structure and forming a channel structure within the holes and within a horizontal space made by removal of the sacrificial layer.

    Nonvolatile memory device and method for fabricating the same
    6.
    发明授权
    Nonvolatile memory device and method for fabricating the same 有权

    公开(公告)号：US11910611B2

    公开(公告)日：2024-02-20

    申请号：US17507989

    申请日：2021-10-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong Hoon Jang ,  Woo Sung Yang ,  Joon Sung Lim ,  Sung Min Hwang

    IPC: H10B43/40 ,  H01L23/522 ,  H10B43/27 ,  H10B43/10

    CPC classification number: H10B43/40 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/27

    Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11139314B2

    公开(公告)日：2021-10-05

    申请号：US16686967

    申请日：2019-11-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung Min Hwang ,  Joon Sung Lim ,  Woo Sung Yang ,  Dong Sik Lee

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

    Abstract: A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200227435A1

    公开(公告)日：2020-07-16

    申请号：US16686967

    申请日：2019-11-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung Min Hwang ,  Joon Sung Lim ,  Woo Sung Yang ,  Dong Sik Lee

    IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573

    Abstract: A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.

Patent Agency Ranking