公开(公告)号：US10361170B2

公开(公告)日：2019-07-23

申请号：US15837187

申请日：2017-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungeun Pyo ,  Jongbo Shim ,  Ji Hwang Kim ,  Chajea Jo ,  Sang-Uk Han

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package including a first substrate including first upper pads, the first upper pads on a top surface of the first substrate, a second substrate including second upper pads, the second upper pads on a top surface of the second substrate, a pitch of the second upper pads being less than a pitch of the first upper pads, and a first semiconductor chip on and electrically connected to both (i) at least one of the first upper pads and (ii) at least one of the second upper pads may be provided.

公开(公告)号：US20240096840A1

公开(公告)日：2024-03-21

申请号：US18370283

申请日：2023-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsu Lee ,  Jongbo Shim ,  Sungeun Pyo

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L24/08 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0801 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1434 ,  H10B80/00

Abstract: A semiconductor device includes a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view; a first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first active layer; a second chip connection pad on the second surface of the first semiconductor substrate and connected to the first through electrode; a first dummy pattern positioned outside the second chip connection pad on the second surface of the first semiconductor substrate from the plan view, the first dummy pattern comprising a line pattern extending horizontally along the second surface of the first semiconductor substrate; and a first chip connection pad on the first surface of the first semiconductor substrate and connected to the first through electrode. The first dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the first semiconductor substrate from the plan view.

公开(公告)号：US20210257305A1

公开(公告)日：2021-08-19

申请号：US17024852

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jungsoo Byun ,  Jongbo SHIM ,  Doohwan Lee ,  Kyoungsei Choi ,  Junggon Choi ,  Sungeun Pyo

IPC: H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.

公开(公告)号：US20240079285A1

公开(公告)日：2024-03-07

申请号：US18316682

申请日：2023-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongmin Kang ,  Jongbo Shim ,  Ji-Yong Park ,  Choongbin Yim ,  Sungeun Pyo

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/3128 ,  H01L21/56 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate, a first semiconductor chip on the first substrate, a molding layer on the first substrate and the first semiconductor chip and has a plurality of recesses, a plurality of substrate connection terminals on the first substrate and in the plurality of recesses, and a second semiconductor chip on the plurality of substrate connection terminals. The plurality of recesses and the plurality of substrate connection terminals are horizontally spaced apart from the first semiconductor chip. The molding layer is spaced apart from the second semiconductor chip.

公开(公告)号：US11581263B2

公开(公告)日：2023-02-14

申请号：US17024852

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jungwoo Kim ,  Jihwang Kim ,  Jungsoo Byun ,  Jongbo Shim ,  Doohwan Lee ,  Kyoungsei Choi ,  Junggon Choi ,  Sungeun Pyo

IPC: H01L23/495 ,  H01L23/538 ,  H01L25/10

Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.